• Skip to primary navigation
  • Skip to main content
  • Skip to footer
  • enEnglish
  • Investor Relations
  • Resource Library
  • Newsroom
  • Blog
  • Careers
  • Support Center
Rambus Logo

Rambus

At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.

  • Products
      • All
          • Interface IP
          • Memory PHYs
          • GDDR6 PHY
          • HBM2E PHY
          • DDR4 PHY
          • More…
          • SerDes PHYs
          • PCIe 5.0 PHY
          • PCIe 4.0 PHY
          • 112G LR PHY
          • 112G XSR PHY
          • 56G PHY
          • 32G PHY
          • 28G PHY
          • More…
          • Northwest Logic Controllers
          • Memory Controllers
          • PCI Express Controllers
          • MIPI Controllers
          • Security IP
          • Root of Trust Solutions
          • Provisioning and Key Management
          • CryptoManager Provisioning
          • CryptoManager Device Key Management
          • Protocol Engines
          • MACsec Engines
          • Multi-Protocol Engines
          • Crypto Accelerator Cores
          • DPA Resistant Cores
          • Basic Crypto Blocks
          • DPA Countermeasures
          • Software Protocols & Crypto Toolkits
          • Anti-Counterfeiting
          • Memory Interface Chips
          • Server DIMM Chipsets
          • DDR5 DIMM Chipset
          • DDR4 NVRCD
          • DDR4 Register Clock Driver
          • DDR4 Data Buffer
          • More…
      • Interface IP
          • Memory PHYs
            • GDDR6 PHY
            • HBM2E PHY
            • DDR4 PHY
            • DDR4 Multi-modal PHY
            • DDR3 PHY
          • SerDes PHYs
            • PCIe 5.0 PHY
            • PCIe 4.0 PHY
            • 112G LR PHY
            • 112G XSR PHY
            • 56G PHY
            • 32G PHY
            • 28G PHY
            • 16G PHY
            • 12G PHY
            • 6G PHY
          • Northwest Logic Controllers
            • PCIe 5.0 Controller
            • PCIe 4.0 Controller
            • HBM2E Controller
            • GDDR6 Controller
            • LPDDR4 Controller
            • DDR4 Controller
            • DDR3 Controller
            • MIPI DSI-2 Controller Core
            • MIPI CSI-2 Controller Core

        • With their reduced power consumption and industry-leading data rates, our line-up of memory interface IP solutions support a broad range of industry standards with improved margin and flexibility. Learn more about our Interface IP solutions
      • Security IP
          • Root of Trust
          • Provisioning and Key Management
            • CryptoManager Provisioning
            • CryptoManager Device Key Management
            • Secure Silicon Provisioning
            • Secure Device Provisioning
          • Protocol Engines
            • MACsec Engines
            • Multi-Protocol Engines for IPsec, TLS and SSL
            • High Speed Public Key Accelerator
          • Crypto Accelerator Cores
            • DPA Resistant Cores
            • Basic Crypto Blocks
          • Anti-Counterfeiting
            • CryptoFirewall Cores
            • Circuit Camouflage Technology
          • DPA Countermeasures
            • DPA Resistant Cores
            • DPA Resistant Software Libraries
            • DPA Workstation Platform
          • Software Protocols & Crypto Toolkits
            • Cloud-optimized IPsec Toolkit
            • Secure Communication Toolkits
            • IoT Security Framework
          • CryptoMedia
            • Content Protection Core
            • Content Protection Services

        • From chip-to-cloud-to-crowd, Rambus secure silicon IP helps protect the world’s most valuable resource: data. Securing electronic systems at their hardware foundation, our embedded security solutions span areas including root of trust, tamper resistance, content protection and trusted provisioning. Learn more about our Security IP offerings
      • Memory Interface Chips
        • Server DIMM Chipsets
          • DDR5 DIMM Chipset
          • Non-Volatile DDR4 Registering Clock Driver
          • DDR4 Register Clock Driver
          • DDR4 Data Buffer
          • DDR3 Register Clock Driver
          • DDR3 Isolation Memory Buffer

        • Made for high speed, reliability and power efficiency, our DDR3, DDR4, and DDR5 chipsets for RDIMM and LRDIMM server modules deliver top-of-the-line performance and capacity for the next wave of enterprise and data center servers. Learn more about our Memory Interface Chip solutions
  • Markets
      • AI & Machine Learning
        • Speed and Security for the Artificial Intelligence & Machine Learning Revolution
          • Products
          • SerDes PHYs
          • Memory PHYs
          • Digital Controllers
          • Memory Interface Chips
          • Root of Trust
          • Crypto Accelerator Cores
          • Protocol Engines
          • Provisioning and Key Management
          • AI & Machine Learning
      • Automotive
        • Providing Performance & Security for the Connected Car
          • Products
          • Memory PHYs
          • SerDes PHYs
          • Digital Controllers
          • Root of Trust
          • PKE Engine
          • MACsec Engines
          • Crypto Accelerator Cores
          • Provisioning and Key Management
          • Explore Automotive
      • Data Center
        • Optimizing capacity, connectivity and capability of the cloud
          • Products
          • SerDes PHYs
          • Memory PHYs
          • Digital Controllers
          • Memory Interface Chips
          • Root of Trust
          • MACsec Engines
          • Software Protocols
          • Provisioning and Key Management
          • See Data Center
      • Edge
        • Catching a tidal wave of data
          • Products
          • Memory PHYs
          • SerDes PHYs
          • Digital Controllers
          • Root of Trust
          • Crypto Accelerator Cores
          • Protocol Engines
          • Software Protocols
          • Discover Edge
      • Government
        • Securing Mission-critical Systems
          • Products
          • Root of Trust
          • Protocol Engines
          • Anti-Tamper Cores
          • Provisioning and Key Management
          • DPA Workstation Platform
          • SerDes PHYs
          • Memory PHYs
          • Digital Controllers
          • See Government
      • IoT
        • Making IoT Data Safe & Fast
          • Products
          • Root of Trust
          • TLS Toolkits
          • Provisioning and Key Management
          • Memory PHYs
          • SerDes PHYs
          • Digital Controllers
          • Explore IoT
  • Resources
    • Inventions
    • Buying Guide
    • Resource Library
      • Webinars
  • About
      • Corporate Overview
      • Leadership
      • Inventors
      • Careers
      • Locations
      • Investor Relations
      • Newsroom
      • Blog
      • Events
      • Partnerships
      • Corporate Social Responsibility
      • Contact

CT-RSA 2017

CT-RSA 2017

RSA Conference Cryptographers’ Track
San Francisco, February 14-17, 2017

Held in conjunction with RSA Conference USA

CT-RSA 2017 Accepted Papers

Call for Papers

Original research papers pertaining to all aspects of cryptography are solicited. Topics include but are not limited to:

  • Public-key algorithms
  • Symmetric-key algorithms
  • Hash functions and MAC algorithms
  • Random Number Generators
  • Cryptographic protocols
  • Cryptographic standards
  • Efficient implementations
  • Elliptic-curve cryptography
  • Post-quantum cryptography
  • CryptoCurrencies and blockchain
  • E-voting
  • Cryptanalysis
  • Hardware security
  • Tamper-resistance
  • Side-channel attacks and defenses
  • White-box cryptography

CT-RSA 2017 Accepted Papers

Gauss Sieve Algorithm on GPUs
Shang-Yi Yang; Po-Chun Kuo; Bo-Yin Yang; Chen-Mou Cheng

Constructions Secure against Receiver Selective Opening and Chosen Ciphertext Attacks
Dingding Jia; Xianhui Lu; Bao Li

Full Disk Encryption: Bridging Theory and Practice
Louiza Khati; Nicky Mouha; Damien Vergnaud

Surnaming Schemes, Fast Verification, and Applications to SGX Technology
Dan Boneh; Shay Gueron

Impossible-Differential and Boomerang Cryptanalysis of Round-Reduced Kiasu-BC
Christoph Dobraunig; Eik List

A Bounded-Space Near-Optimal Key Enumeration Algorithm for Multi-Subkey Side-Channel Attacks
Liron David; Avishai Wool

Improved Key Recovery Algorithms from Noisy RSA Secret Keys with Analog Noise
Noboru Kunihiro; Yuki Takahashi

Encoding-Free ElGamal-type Encryption Schemes on Elliptic Curves
Marc Joye; Benoît Libert

On the Entropy of Oscillator-Based True Random Number Generators
Yuan Ma; Jingqiang Lin; Jiwu Jing

My Traces Learn What You Did in the Dark: Recovering Secret Signals without Key Guesses
Si Gao; Hua Chen; Wenling Wu; Limin Fan; Weiqiong Cao; Xiangliang Ma

An Efficient Side-Channel Protected AES Implementation with Arbitrary Protection Order
Hannes Gross; Stefan Mangard; Thomas Korak

Revisiting Full-PRF-Secure PMAC and Using It for Beyond-Birthday Authenticated Encryption
Eik List; Mridul Nandi

Weak Keys for AEZ, and the External Key Padding Attack
Bart Mennink

Low-Leakage Secure Search for Boolean Expressions
Fernando Krell; Gabriela Ciocarlie; Ashish Gehani; Mariana Raykova

Ridge-based Profiled Differential Power Analysis
Weijia Wang; Yu Yu; François-Xavier Standaert; Dawu Gu; Sen Xu; Chi Zhang

Feeding Two Cats with One Bowl: On Designing a Fault and Side-Channel Resistant Software Encoding Scheme
Jakub Breier; Xiaolu Hou

Hiding Higher-Order Side-Channel Leakage – Randomizing Cryptographic Implementations in Reconfigurable Hardware
Pascal Sasdrich; Amir Moradi; Tim Güneysu

Publish or Perish: A Backward-Compatible Defense against Selfish Mining in Bitcoin
Ren Zhang; Bart Preneel

WEM: A New Family of White-box Block Ciphers Based on the Even-Mansour Construction
Jihoon Cho; Kyu Young Choi; Itai Dinur; Orr Dunkelman; Nathan Keller; Dukjae Moon; Aviya Veidberg

New Revocable IBE in Prime-Order Groups: Adaptively Secure, Decryption Key Exposure Resistant, and with Short Public Parameters
Yohei Watanabe; Keita Emura; Jae Hong Seo

Actively Secure 1-out-of-N OT Extension with Application to Private Set Intersection
Michele Orru; Emmanuela Orsini; Peter Scholl

Time-Memory Trade-offs for Side-channel Resistant Implementations of Block Ciphers
Praveen Kumar Vadnala

Choosing Parameters for NTRUEncrypt
Jeff Hoffstein; Jill Pipher; John Schanck; Joseph H. Silverman; William Whyte; Zhenfei Zhang

Provably Secure Password Authenticated Key Exchange Based on RLWE for the Post-Quantum World
Jintai Ding; Saed Alsayigh; Jean Lancrenon; Saraswathi RV; Michael Snook

A Tool Kit for Partial Key Exposure Attacks on RSA
Atsushi Takayasu; Noboru Kunihiro

Important Dates

Submission Deadline: September 3, 2016 — 23:59 PDT (UTC-7)
Notification : November 7, 2016
Final Version of the Paper : November 21, 2016

All papers accepted for presentation will appear in the conference proceedings and will be published in the Lecture Notes in Computer Science series (www.springer.com/lncs). Authors of accepted papers must make their paper available online.

Submission Instructions

All submissions should be uploaded to the WebReview system at https://secure.iacr.org/websubrev/ctrsa2017/submit/ in pdf format by the September 3rd deadline.

Submissions must not substantially duplicate work that any of the authors has published in a journal or in a conference or workshop with proceedings, or has submitted or is planning to submit before the author notification deadline to a journal or other conferences or workshops that have proceedings. Accepted submissions may not appear in any other conference or workshop that has proceedings.
Submissions must be anonymous, with no author names, affiliations, acknowledgments, or obvious references. Each submission should begin with a title, a short abstract, and a list of keywords. Submissions should be at most 16 pages including the bibliography and should use the Springer LNCS format with no changes to the margins or fonts. Supplementary materials may be appended without a page limit, but reviewers are not required to read them. Submissions should be intelligible and self-contained within the 16 page bound. The same bound will be applied to those papers accepted for publication in the proceedings. Submissions not meeting these guidelines risk rejection without consideration of their merits.

Authors should report any “conflicts” with program committee members listed below. A conflict exists if an author and committee member have the same affiliation or have been co-authors on a paper within the past two years.

Program Committee

Josh BenalohMicrosoft Research, USA
Alex BiryukovUniversity of Luxembourg, Luxembourg
Chen-Mou ChengOsaka University, Japan
Jeremy ClarkConcordia University, Canada
Jean Paul DegabrieleRoyal Holloway University of London, UK
Orr DunkelmanUniversity of Haifa, Israel
Junfeng FanOpen Security Research, China
Henri GilbertANSSI, France
Tim GüneysuUniversity of Bremen and DFKI, Germany
Helena Handschuh (Chair)Rambus Cryptography Research, USA
Stanislaw JareckiUniversity of California at Irvine, USA
Thomas JohanssonLund University, Sweden
Marc JoyeNXP Semiconductors, USA
Kwangjo KimKAIST, Republic of Korea
Susan LangfordHewlett-Packard Company, USA
Tancrede LepointSRI International, USA
Stefan MangardGraz University of Technology, Austria
Mitsuru MatsuiMitsubishi Electric, Japan
David M’RaïhiSymphony, USA
Maria Naya PlasenciaINRIA, France
Kaisa NybergAalto University (retired), Finland
Elisabeth OswaldUniversity of Bristol, UK
Raphael PhanMultimedia University, Malaysia
David PointchevalÉcole Normale Supérieure, France
Bart PreneelKULeuven and iMinds, Belgium
Matt RobshawImpinj, USA
Rei Safavi-NainiUniversity of Calgary, Canada
Kazue SakoNEC, Japan
Palash SarkarIndian Statistical Institute, India
Nigel SmartUniversity of Bristol, UK
Marc StevensCWI, The Netherlands
Willy SusiloUniversity of Wollongong, Australia
Huaxiong WangNanyang Technological University, Singapore
Brecht WyseurNagra, Switzerland

 

Footer

About

  • Corporate Overview
  • Leadership
  • Careers
  • Locations
  • Investor Relations
  • News
  • Corporate Social Responsibility

Products

  • Memory PHYs
  • SerDes PHYs
  • Northwest Logic Controllers
  • Server DIMM Chipsets
  • Root of Trust Solutions
  • Provisioning and Key Management
  • Protocol Engines
  • Crypto Accelerator Cores
  • Software Protocols
  • DPA Countermeasures
  • Anti-Counterfeiting
  • CryptoMedia

Markets

  • AI & Machine Learning
  • Automotive
  • Data Center
  • Edge
  • Government
  • IoT
  • Pay TV

Resources

  • Resource Library
  • Webinars
  • Inventions
  • Buying Guide
  • Contact

Copyright © 2021 Rambus.com. All Rights Reserved. Privacy Policy | Trademark & Guidelines

  • Facebook icon
  • Twitter icon
  • YouTuve icon
  • LinkedIn icon
  • Blog icon