Join us for D&R IP SoC China! Stop by and say hi to our experts, and join us for two presentations.
Title: From Monolithic SoCs to Chiplets: A New Hardware Security Paradigm
Speaker: Samuel Chiang, Director of Business Development, APAC at Rambus
Abstract: Chiplet‑based architectures are transforming SoC design, but they also upend long‑standing security assumptions. By disaggregating a monolithic die into multiple, often multi‑vendor chiplets, the implicit silicon trust boundary disappears, expanding the attack surface to include chiplet substitution, weak‑chiplet compromise, and exposed die‑to‑die interconnects. This presentation explores why traditional SoC security models fail in chiplet systems and introduces a system‑level security paradigm based on distributed trust with centralized authority.
Title: AI Inference Needs a Mix-and-Match Memory Strategy
Speaker: Kai Zhao, SPE Field Applications Engineering
Abstract: AI inference spans diverse workloads, from low‑latency chat to long‑context reasoning and large‑scale recommendations—making single, monolithic accelerator and memory designs increasingly inefficient. This talk explains how inference naturally splits into prefill and decode stages with fundamentally different bottlenecks: prefill is compute‑bound, while decode is dominated by memory bandwidth and latency. By matching memory technologies to each stage, using cost‑efficient GDDR or LPDDR for prefill and reserving premium HBM for decode, with pooled memory for KV offload, operators can significantly reduce cost per token without sacrificing latency. The session outlines emerging disaggregated architectures for AI inference workloads.
To learn more and register, visit the event page here: https://www.design-reuse-embedded.com/ipsocdays/2026/china/
