Interface IP chip icon

Interface IP

DDR4 Controller

The Northwest Logic DDR4 controller core is designed for high memory throughput, high clock rates, and full programmability in computing and networking applications. With the Rambus DDR4 PHY, it comprises a complete DDR4 memory interface subsystem.

How the DDR4 Interface works

The Northwest Logic DDR4 controller maximizes memory bus efficiency via Look-Ahead command processing, bank management, auto-precharge and additive latency support. The core is DFI compatible and supports a range of interfaces to user logic.

The Rambus DDR4 memory PHY delivers industry-leading data rates of up to 3200 Mbps and is compatible with the DDR4 and DDR3 standards. The PHY consists of a Command/Address (C/A) macro cell and Data (DQ) macro cells configured to create a 72-bit wide channel.

DDR4 Memory Interface Subsystem
DDR4 Memory Interface Subsystem

The Rambus DDR4 PHY and Northwest Logic DDR4 controller used together comprise a complete DDR4 memory interface subsystem. Alternatively, these cores can be licensed separately to be paired with 3rd-party DDR4 controller or PHY solutions.

Data Center to End Device: AI/ML Inferencing with GDDR6 cover

From Data Center to End Device: AI/ML Inferencing with GDDR6

Created to support 3D gaming on consoles and PCs, GDDR packs performance that makes it an ideal solution for AI/ML inferencing. As inferencing migrates from the heart of the data center to the network edge, and ultimately to a broad range of AI-powered IoT devices, GDDR memory’s combination of high bandwidth, low latency, power efficiency and suitability for high-volume applications will be increasingly important. The latest iteration of the standard, GDDR6 memory, pushes data rates to 18 gigabits per second and device bandwidths to 72 gigabytes per second.

Solution Offerings

  • Maximizes bus efficiency via look-ahead command processing, bank management, auto-precharge and additive latency support
  • Latency minimized via parameterized pipelining
  • Achieves high clock rates with minimal routing constraints
  • Supports half-rate and quarter-rate clock operation
  • Supports DDR4 SDRAM 3DS device configurations
  • Multi-mode controller support
  • Full run-time configurable timing parameters and memory settings
  • DFI compatible
  • Full set of Add-On cores available
  • RDIMM and LRDIMM support
  • Minimal ASIC gate count
  • Delivered fully integrated and verified with target PHY
  • Core (source code)
  • Testbench (source code)
  • Complete documentation
  • Expert technical support
  • Maintenance updates

Engineering Design Services:

  • Customization
  • SoC integration

Protocol Compatibility

ProtocolData Rate (Mbps) Max. Application
DDR41600 to 3200Data Center, Edge