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Interface IP

HBM2 Controller

The Northwest Logic HBM2 controller core is designed for use in applications requiring high memory throughput including performance-intensive applications in artificial intelligence (AI), data center and graphics. With the Rambus HBM2 PHY it comprises a complete HBM2 memory interface subsystem.

How the HBM2 Interface works

HBM is a high-performance memory that features reduced power consumption and a small form factor.  It combines 2.5D packaging with a wider interface at a lower clock speed (as compared to DDR4) to deliver higher overall throughput at a higher bandwidth-per-watt efficiency for high-performance computing applications.

The Rambus HBM2 PHY is fully compliant to the JEDEC HBM2 standard and supports data rates up to 2 Gbps per data pin, resulting in a total bandwidth of 256 GB/s. The interface features 8 independent channels, each containing 128 bits for a total data width of 1024 bits, and support for a stack height of 2, 4 or 8 DRAMs. In addition, the PHY is designed for a 2.5D system with an interposer for routing signals between the DRAM and PHY. This combination of signal density and stacked form factor requires special design consideration. In order to enable easy implementation and improved flexibility of design in such a complex system, Rambus performs complete signal and power integrity analysis on the entire 2.5D system to ensure that all signal, power and thermal requirements are met.

HBM2 Memory Interface Subsystem Example
HBM2 Memory Interface Subsystem Example

The Northwest Logic HBM2 Controller supports both HBM2 and HBM2E devices with data rates of up to 3.2 Gbps per data pin. It supports all standard channel densities including 4, 6, 8, 12, 16 and 24 Gb. The controller maximizes memory bandwidth and minimizes latency via Look-Ahead command processing. The core is DFI compatible (with extensions added for HBM2) and supports AXI, OCP or native interface to user logic.

The Rambus HBM2 PHY and Northwest Logic HBM2 controller used together comprise a complete HBM2 memory interface subsystem. Alternatively, these cores can be licensed separately to be paired with 3rd-party HBM2 controller or PHY solutions.

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Solution Offerings

  • Supports HBM2 and HBM2E devices
  • Supports all standard HBM2 channel densities (4, 6, 8, 12, 16, 24 Gb)
  •  Supports up to 3.2 Gbps/pin
  •  Can handle two pseudo-channels with one controller or independently with two controllers
  • Queue-based interface optimizes performance and throughput
  • Maximizes memory bandwidth and minimizes latency via Look-Ahead command processing
  • Achieves high clock rates with minimal routing constraints
  • Full run-time configurable timing parameters and memory settings
  • DFI compatible (with extensions added for HBM2)
  • Full set of Add-On cores available
  • Supports AXI, OCP or native interface to user logic
  • Delivered fully integrated and verified with target PHY
  • Core (source code)
  • Testbench (source code)
  • Complete documentation
  • Expert technical support
  • Maintenance updates
 

Engineering Design Services:

  • Customization
  • SoC Integration

Protocol Compatibility

ProtocolData Rate (Gbps) Max. Application
HBM22AI, Data Center, Graphics
HBM2E3.2AI, Data Center, Graphics

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