HBM2E Controller

How the HBM2E Interface works

HBM2E is a high-performance memory that features reduced power consumption and a small form factor.  It combines 2.5D packaging with a wider interface at a lower clock speed (as compared to GDDR6) to deliver higher overall throughput at a higher bandwidth-per-watt efficiency for AI/ML and HPC applications.

The Northwest Logic HBM2E controller supports both HBM2 and HBM2E devices with data rates of up to 3.6 Gbps per data pin. It supports all standard channel densities including 4, 6, 8, 12, 16 and 24 Gb. The controller maximizes memory bandwidth and minimizes latency via Look-Ahead command processing. The core is DFI compatible (with extensions added for HBM2E) and supports AXI, OCP or native interface to user logic.

The Rambus HBM2E interface is fully compliant with the JEDEC HBM2E JESD235 standard. It supports data rates up to 3.6 Gbps per data pin. The interface features 8 independent channels, each containing 128 bits for a total data width of 1024 bits. The resulting bandwidth is 461 GB/s per stack, with the stack consisting of 2, 4, 8 or 12 DRAMs.

The interface is designed for a 2.5D system with an interposer used for routing signals between the 3D DRAM stack and the PHY on the SoC. This combination of signal density and stacked form factor requires special design consideration. In order to enable easy implementation and improved flexibility of design, Rambus performs complete signal and power integrity analysis on the entire 2.5D system to ensure that all signal, power and thermal requirements are met.