HBM3 is a high-performance memory that features reduced power consumption and a small form factor. It combines 2.5D packaging with a wider interface at a lower clock speed (as compared to GDDR6) to deliver higher overall throughput at a higher bandwidth-per-watt efficiency for AI/ML and high-performance computing (HPC) applications.
The Rambus HBM3 memory subsystem supports data rates up to 8.4 Gbps per data pin. The interface features 16 independent channels, each containing 64 bits for a total data width of 1024 bits. At maximum data rate, this provides a total interface bandwidth of 1075.2 GB/s.
The interface is designed for a 2.5D system with an interposer used for routing signals between the 3D DRAM stack and the memory subsystem on the SoC. This combination of signal density and stacked form factor requires special design consideration. In order to enable easy implementation and improved flexibility of design, Rambus performs complete signal and power integrity analysis on the entire 2.5D system to ensure that all signal, power and thermal requirements are met.
The Rambus HBM3 memory subsystem supports HBM3 memory devices with 2, 4, 8, 12 and 16 DRAM stack height with densities of up 32 Gb. The subsystem maximizes bandwidth and latency via Look-Ahead command processing.
The Rambus HBM3 memory subsystem comprises an integrated HBM3 PHY and Controller. Alternatively, these cores can be licensed separately to be paired with 3rd-party HBM3 controller or PHY solutions.
For AI and HPC applications, HBM2E memory can deliver excellent bandwidth, capacity and latency in a very compact footprint thanks to its 2.5D/3D structure. The flipside is that this same structure leads to greater design complexity and raises a new set of implementation considerations.
|Protocol||Data Rate (Gbps) Max.||Application|
|HBM3||4.8, 5.6, 6.4, 8.4||AI/ML, HPC, Data Center, Graphics|
CSI – DSI Demonstration (Rambus MIPI Fidus Inrevium FMC)