The LPDDR4 controller core accepts commands using a simple local interface and translates them to the command sequences required by LPDDR4 devices. The core also performs all initialization, refresh and power-down functions.
The core uses bank management modules to monitor the status of each LPDDR bank. Banks are only opened or closed when necessary, minimizing access delays.
The core queues up multiple commands in the command queue. This enables optimal bandwidth utilization for both short transfers to highly random address locations as well as longer transfers to contiguous address space. The command queue is also used to opportunistically perform look-ahead activates, precharges and auto-precharges further improving overall throughput.
The core is provided with run-time programmable inputs for all memory timing parameters and configuration settings. This ensures compatibility with all LPDDR4 configurations.
Add-On Cores such as a Multi-Port Front-End and Reorder Core can be optionally delivered with the core. The core is delivered fully integrated and verified with the target LPDDR PHY.
|Protocol||Data Rate (Gbps)||Application|
|LPDDR4||3.2||Mobile, Automotive, AI|
CSI – DSI Demonstration (Rambus MIPI Fidus Inrevium FMC)