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Interface IP

CSI-2 Controller Core

The Northwest Logic CSI-2 controller core is a second-generation MIPI CSI-2 core optimized for high performance, low power and small size. The core is fully compliant with the CSI-2 standard and implements all three layers defined therein: Pixel to Byte Packing, Low Level Protocol, and Lane Management.

CSI-2 Controller V2 Block Diagram (Receive Version)
CSI-2 Controller V2 Block Diagram (Receive Version)
Going Beyond GPUs with GDDR6

Going Beyond GPUs with GDDR6

Supported by Micron Technology, SK Hynix and Samsung, GDDR6 SGRAM will feature a maximum data transfer rate of 16 Gbps, along with an operating voltage of 1.35V. GDDR6 offers higher densities compared to previous-generation graphics memory. In addition, GDDR6 doubles the speed (12–16 Gb/s) of GDDR5 and provides more than 5X the 3.2 Gb/s speed of DDR4. Although initially targeted at game consoles and PC graphics, the latest iteration of GDDR is expected to be deployed across multiple verticals, with Micron specifically highlighting the data center and automotive sector.

Solution Offerings

  • Fully CSI-2 standard compliant
  • 64 and 32-bit core widths
  • Transmit and Receive versions
  • Supports 1-8, 2.5+ Gbps D-PHY data lanes
  • Supports 1-4, 2.5+ Gsym/s C-PHY lane (trio)
  • Supports all data types
  • Easy-to-use pixel-based interface
  • Optional AXI interface (Rx only)
  • Optional video interface
  • Delivered fully integrated and verified with target MIPI PHY
  • Complete FPGA-based demonstration system available
  • Core (source code)
  • Testbench (source code)
  • Complete documentation
  • Expert technical support
  • Maintenance updates

Engineering Design Services:

  • Customization
  • SoC integration

Protocol Compatibility

ProtocolData Rate (Gbps) Application
CSI-22.5+Mobile, IoT
The Rambus GDDR6 PHY IP Core thumbnail

The Rambus GDDR6 PHY IP Core

The JEDEC-compliant Rambus GDDR6 PHY IP Core is optimized for systems that require low-latency and high-bandwidth GDDR6 memory solutions. Available on leading FinFET process nodes, the PHY interface supports two independent channels, with each supporting 16 bits for a total data width of 32 bits. In addition, the PHY supports speeds up to 16Gbps per pin, providing a maximum bandwidth of up to 64 GB/s.