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Interface IP

PLDA PCIe 5.0 Controller

The PLDA PCIe 5.0 Controller (formerly XpressRICH) is designed to achieve maximum PCI Express (PCIe) 5.0 performance with great design flexibility and ease of integration. It is fully backward compatible with PCIe 4.0 and 3.1/3.0. A PCIe 5.0 Controller with AXI (formerly XpressRICH-AXI) is also available. The controller the Rambus PCIe 5.0 PHY forms a comprehensive interface subsystem solution delivering high-bandwidth and low-latency connectivity for next-generation applications in artificial intelligence/machine learning (AI/ML), data center, edge, 5G infrastructure and graphics.

How the PCIe 5.0 Controller Works

The PCIe 5.0 Controller is configurable and scalable IP designed for ASIC and FPGA implementation. It supports the PCIe 5.0, 4.0 and 3.1/3.0 specifications, as well as the version 5.x of the PHY Interface for PCI Express (PIPE) specification. The IP can be configured to support endpoint, root port, switch port, and dual-mode topologies, allowing for a variety of use models.

PCIe 5.0 Controller Block Diagram
PCIe 5.0 Controller Block Diagram
PCIe 5.0 Controller with AXI Block Diagram
PCIe 5.0 Controller with AXI Block Diagram
PCIe 5.0 Interface Subsystem solution
PCIe 5.0 Interface Subsystem Solution

The Rambus PCIe 5.0 PHY and PLDA PCIe 5.0 Controller comprise a complete PCIe 5.0 interface subsystem. The PCIe 5 SerDes PHY is available on an advanced 7nm FinFET process node. The PCIe 5.0 controller can be synthesized on any process.

Data Center Evolution: Accelerating Computing with PCI Express 5.0

Data Center Evolution: Accelerating Computing with PCI Express 5.0

The PCI Express® (PCIe) interface is the critical backbone that moves data at high bandwidth between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. The rise of cloud-based computing and hyperscale data centers, along with high-bandwidth applications like artificial intelligence (AI) and machine learning (ML), require the new level of performance of PCI Express 5.0. 

Solution Offerings

Protocol Compatibility

ProtocolSignaling Rate (GT/s) Application
PCIe 3.1/3.08Servers, storage, networking devices
PCIe 4.016Servers, storage, networking devices
PCIe 5.032AI, servers, storage, networking, 5G infrastructure
SerDes Signal Integrity Challenges at 28Gbps and Beyond

SerDes Signal Integrity Challenges at 28Gbps and Beyond

Maintaining signal integrity has become increasingly difficult as data rates moves past 28Gbps to 56Gbps and beyond. Up to 28Gbps rates, NRZ is the preferred and standardized encoding scheme which consists of 1’s and 0’s. NRZ is also referred to as PAM2 (pulse amplitude modulation, 2-level), due to its two amplitude levels which contain 1 bit of information in every symbol. With serial data rates hitting 56 Gb/s per channel, signal impairments caused by increased bandwidth has prompted the high-speed serial data industry to adopt PAM4, or 4-level pulse amplitude modulation. 

Inventions

Phase Interpolator-Based CDR

Reduces cost, power and area of clock and data recovery (CDR) circuit and improves jitter performance in high-speed parallel and serial links versus PLL-based CDRs.

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