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Interface IP

DDR4 Multi-modal PHY

Designed for server, networking, computing and consumer applications, our DDR4 multi-modal memory PHY is optimized for performance and power efficiency while maintaining full compatibility with industry standard DDR4, DDR3, LPDDR3, and LPDDR2 interfaces. This broad compatibility, combined with support for a wide range of data rates, delivers our customers superior design flexibility and ease of integration.

How the DDR4 Multi-modal PHY works

The DDR4 multi-modal PHY is a DFI 3.1 compliant memory interface that supports both UDIMM and RDIMM modules as well as DRAM–on-motherboard topologies, making it suitable for a broad range of enterprise and consumer applications.

DDR4 Multi-modal Subsystem Example
DDR4 Multi-modal Subsystem Example

Our silicon-proven PHY consists of a Command/Address (C/A) block, Clock and Power Management block and Data (DQ) macro cells to create a 72 bits wide channel. It is fully characterized and contains all of the necessary components for robust operation and is available in GF 28SLP and SS 28 LPP processes.

The PHY has also undergone extensive design-phase modeling and simulation to ease implementation.

Solution Offerings

  • PLL-based clocking with internal clock alignment to the parallel clock on the memory controller interface
  • Autonomous initialization
  • Support for x72 bit channel
  • Support for multiple DRAM widths (x4, x8, x16, x32)
  • Support for single channel, 1 to 4 ranks
  • Selectable low-power operating states
  • DFI 3.1 compliant for easy integration with memory controller
  • Programmable output impedance and on-die termination
  • ZQ calibration of output impedance and on-die calibration
  • Utilizes standard 8-layer 6020 metal layer stack
  • Supports package-on-package and C4 flip-chip packaging options
  • Register interface for state observation
  • Test traffic generation and error checking for in-situ test
  • LabStation™ software environment for system level bring-up, characterization, and validation
  • Fully-characterized hard macro (GDSII): optimized for North-South side of SOC Placement
  • North-South side of SOC Placement
  • Complete design views:
    • Gate-level and IO models
    • Verification test benches
    • Layout abstracts (.lef)
    • Timing models (.lib)
  • Memory controller reference design
  • Full Documentation
    • Integration Guidelines
    • Package and PCB design guidelines
    • ASIC/DFT manufacturing guidelines
    • Test and Characterization user guide
    • Verilog models
    • CDL netlists *(.cdl)
    • ATPG models
    • GDSII layout
    • DRC & LVS reports

Comprehensive Chip and System Design Reviews

  • Kickoff/Program Review
  • Floor plan Review
  • Test/Characterization Plan Review
  • Package Design Review
  • Board Design Review
  • Final Chip Integration Review
  • Bring-up and Test Review

Engineering Design Services:

  • Package design
  • System board layout
  • Statistically-based signal and power integrity analysis

Protocol Compatibility

ProtocolData Rate (Gbps) Application
DDR3 (1.5V)800-2133Consumer Electronics
DDR3L (1.35V)800-1866Consumer Electronics
DDR3U (1.25V)800-1866Low-Power Consumer Electronics
LPDDR3e333-2133 Mobile
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FlexPhase™ Timing Adjustment Circuits

FlexPhase per bit timing adjustment circuits deskew data and clock signals to improve signal integrity and simplify package and PCB system design.

Output Driver Calibration

Output driver calibration allows SoC designers to tune the output signaling to optimal levels in order to improve data rates and system voltage margin.

On Die Termination Calibration

ODT calibration enables higher data rates and superior DRAM device and module performance by establishing the optimal termination value to compensate for variations in process and operating conditions that degrade signal performance.