HBM is a high-performance memory that features reduced power consumption and a small form factor. It combines 2.5D packaging with a wider interface at a lower clock speed (as compared to DDR4) to deliver higher overall throughput at a higher bandwidth-per-watt efficiency for high-performance computing applications.
The Rambus HBM2 PHY is fully compliant to the JEDEC HBM2 standard and supports data rates up to 2 Gbps per data pin, resulting in a total bandwidth of 256 GB/s. The interface features 8 independent channels, each containing 128 bits for a total data width of 1024 bits, and support for a stack height of 2, 4 or 8 DRAMs. In addition, the PHY is designed for a 2.5D system with an interposer for routing signals between the DRAM and PHY. This combination of signal density and stacked form factor requires special design consideration. In order to enable easy implementation and improved flexibility of design in such a complex system, Rambus performs complete signal and power integrity analysis on the entire 2.5D system to ensure that all signal, power and thermal requirements are met.
The Northwest Logic HBM2 Controller supports both HBM2 and HBM2E devices with data rates of up to 3.2 Gbps per data pin. It supports all standard channel densities including 4, 6, 8, 12, 16 and 24 Gb. The controller maximizes memory bandwidth and minimizes latency via Look-Ahead command processing. The core is DFI compatible (with extensions added for HBM2) and supports AXI, OCP or native interface to user logic.
The Rambus HBM2 PHY and Northwest Logic HBM2 controller used together comprise a complete HBM2 memory interface subsystem. Alternatively, these cores can be licensed separately to be paired with 3rd-party HBM2 controller or PHY solutions.
Comprehensive Chip and System Design Reviews
Engineering Design Services:
|Protocol||Data Rate (Gbps)||Application|
|HBM2||0.5-2000||Data Center and Networking|
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