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Interface IP

HBM2 PHY

Optimized for the low-latency and high-bandwidth memory applications, the HBM Gen2 (HBM2) PHY delivers maximum performance and flexibility in minimal form factor and power envelope. With the Northwest Logic HBM2 Controller it comprises a complete HBM2 memory interface subsystem.

How the HBM2 Interface works

HBM is a high-performance memory that features reduced power consumption and a small form factor.  It combines 2.5D packaging with a wider interface at a lower clock speed (as compared to DDR4) to deliver higher overall throughput at a higher bandwidth-per-watt efficiency for high-performance computing applications.

The Rambus HBM2 PHY is fully compliant to the JEDEC HBM2 standard and supports data rates up to 2 Gbps per data pin, resulting in a total bandwidth of 256 GB/s. The interface features 8 independent channels, each containing 128 bits for a total data width of 1024 bits, and support for a stack height of 2, 4 or 8 DRAMs. In addition, the PHY is designed for a 2.5D system with an interposer for routing signals between the DRAM and PHY. This combination of signal density and stacked form factor requires special design consideration. In order to enable easy implementation and improved flexibility of design in such a complex system, Rambus performs complete signal and power integrity analysis on the entire 2.5D system to ensure that all signal, power and thermal requirements are met.

HBM2 Memory Interface Subsystem Example
HBM2 Memory Interface Subsystem Example

The Northwest Logic HBM2 Controller supports both HBM2 and HBM2E devices with data rates of up to 3.2 Gbps per data pin. It supports all standard channel densities including 4, 6, 8, 12, 16 and 24 Gb. The controller maximizes memory bandwidth and minimizes latency via Look-Ahead command processing. The core is DFI compatible (with extensions added for HBM2) and supports AXI, OCP or native interface to user logic.

The Rambus HBM2 PHY and Northwest Logic HBM2 controller used together comprise a complete HBM2 memory interface subsystem. Alternatively, these cores can be licensed separately to be paired with 3rd-party HBM2 controller or PHY solutions.

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Solution Offerings

  • Flexible delivery of IP core: works with ASIC/SoC layout requirements
  • Speed bins: 0.5 Gbps, 1.0 Gbps, 1.5 Gbps, 1.6 Gbps, 1.8 Gbps, 2.0 Gbps
  • 8 channels and 16 pseudo-channels
  • Support for DRAM 2, 4, or 8, stacks
  • DFI 3.1 style interface for easy integration with memory controller
  • Memory controller or PHY can be ASIC interface master (PHY independent mode)
  • Selectable low-power operating states
  • Programmable output impedance
  • Pin programmable support for lane repair
  • ZQ calibration of output impedance
  • IEEE 1500 test support
  • Autonomous test support
  • SSO noise reduction
  • Micro-bump pitch matched to the DRAM pitch
  • Utilizes 13-layer metal stack
  • East-West orientation (PHY can be placed in corner of die)
  • Register interface for state observation
  • LabStation™ software environment for system level bring-up, characterization, and validation
  • Fully-characterized hard macro (GDSII)
  • Complete design views:
    • Gate-level and IO models
    • Verification test benches
    • Layout abstracts (.lef)
    • Timing models (.lib)
  • Full documentation:
    • Datasheet
    • Package and interposer design guidelines
    • ASIC/DFT manufacturing guidelines
    • Test and characterization user guide
    • Verilog models
    • CDL netlists (.cdl)
    • GDSII layout
    • DRC & LVS reports

Comprehensive Chip and System Design Reviews

  • Kickoff/Program Review
  • Floor plan Review
  • Test/Characterization Plan Review
  • Package Design Review
  • Board Design Review
  • Final Chip Integration Review
  • Bring-up and Test Review

Engineering Design Services:

  • Package design
  • System board layout
  • Statistically-based signal and power integrity analysis

Protocol Compatibility

ProtocolData Rate (Gbps) Application
HBM20.5-2000Data Center and Networking

Inventions

Phase Interpolator-Based CDR

Reduces cost, power and area of clock and data recovery (CDR) circuit and improves jitter performance in high-speed parallel and serial links versus PLL-based CDRs.

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