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Interface IP

HBM2E PHY

Optimized for high bandwidth and low latency, the HBM2E PHY delivers maximum performance and flexibility in a compact form factor and power-efficient envelope. With the co-verified Northwest Logic HBM2E Controller it comprises a complete HBM2E memory interface subsystem.

How the HBM2E Interface works

HBM2E is a high-performance memory that features reduced power consumption and a small form factor.  It combines 2.5D packaging with a wider interface at a lower clock speed (as compared to DDR4) to deliver higher overall throughput at a higher bandwidth-per-watt efficiency for AI/ML and high-performance computing (HPC) applications.

The Rambus HBM2E interface is fully compliant with the JEDEC JESD235B standard. It supports data rates up to 3.2 Gbps per data pin. The interface features 8 independent channels, each containing 128 bits for a total data width of 1024 bits. The resulting bandwidth is 410 GB/s per stack, with the stack consisting of 2, 4, 8 or 12 DRAMs.

The interface is designed for a 2.5D system with an interposer used for routing signals between the DRAM stack and the PHY on the SoC. This combination of signal density and stacked form factor requires special design consideration. In order to enable easy implementation and improved flexibility of design, Rambus performs complete signal and power integrity analysis on the entire 2.5D system to ensure that all signal, power and thermal requirements are met.

HBM2E Memory Interface Subsystem Example
HBM2E Memory Interface Subsystem Example

The Northwest Logic HBM2E controller supports both HBM2 and HBM2E devices with data rates of up to 3.2 Gbps per data pin. It supports all standard channel densities including 4, 6, 8, 12, 16 and 24 Gb. The controller maximizes memory bandwidth and minimizes latency via Look-Ahead command processing. The core is DFI compatible (with extensions added for HBM2E) and supports AXI, OCP or native interface to user logic.

The HBM2E PHY and Northwest Logic HBM2E controller used together comprise a complete HBM2E memory interface subsystem. Alternatively, these cores can be licensed separately to be paired with 3rd-party HBM2E controller or PHY solutions.

Download HBM2 and GDDR6: Memory Solutions for AI white paper

HBM2E and GDDR6: Memory Solutions for AI

Artificial Intelligence/Machine Learning (AI/ML) growth proceeds at a lightning pace. In the past eight years, AI training capabilities have jumped by a factor of 300,000 driving rapid improvements in every aspect of computing hardware and software. Meanwhile, AI inference is being deployed across the network edge and in a broad spectrum of IoT devices including in automotive/ADAS. Training and inference have unique feature requirements that can be served by tailored memory solutions. Learn how HBM2E and GDDR6 provide the high performance demanded by the next wave of AI applications.

Solution Offerings

  • Co-verified with available Northwest Logic HBM2E controller
  • Flexible delivery of IP core: works with ASIC/SoC layout requirements
  • Speed bins: 0.5, 1.0, 1.5, 1.6, 1.8, 2.0, 2.4, 3.0, 3.2 Gbps
  • 8 channels and 16 pseudo-channels
  • Support for stacks of 2, 4, 8 or 12 DRAM
  • DFI 3.1 style interface for easy integration with memory controller
  • Memory controller or PHY can be ASIC interface master (PHY independent mode)
  • Selectable low-power operating states
  • Programmable output impedance
  • Pin programmable support for lane repair
  • ZQ calibration of output impedance
  • IEEE 1500 test support
  • Autonomous test support
  • SSO noise reduction
  • Micro-bump pitch matched to the DRAM pitch
  • Utilizes 13 or 15-layer metal stack
  • East-West orientation (PHY can be placed in corner of die)
  • Register interface for state observation
  • LabStation™ software environment for system level bring-up, characterization, and validation
  • Fully-characterized hard macro (GDSII)
  • Complete design views:
    • Gate-level and IO models
    • Verification test benches
    • Layout abstracts (.lef)
    • Timing models (.lib)
  • Full documentation:
    • Datasheet
    • Package and interposer design guidelines
    • ASIC/DFT manufacturing guidelines
    • Test and characterization user guide
    • Verilog models
    • CDL netlists (.cdl)
    • GDSII layout
    • DRC & LVS reports

Comprehensive Chip and System Design Reviews

  • Kickoff/Program Review
  • Floor plan Review
  • Test/Characterization Plan Review
  • Package Design Review
  • Board Design Review
  • Final Chip Integration Review
  • Bring-up and Test Review

Engineering Design Services:

  • Package design
  • System board layout
  • Statistically-based signal and power integrity analysis
2.5D/3D Packaging Solutions for AI and HPC

2.5D/3D Packaging Solutions for AI and HPC

For AI and HPC applications, HBM2E memory can deliver excellent bandwidth, capacity and latency in a very compact footprint thanks to its 2.5D/3D structure. The flipside is that this same structure leads to greater design complexity and raises a new set of implementation considerations.

Protocol Compatibility

ProtocolData Rate (Gbps) Application
HBM2E0.5-3.2AI/ML, HPC and Data Center
HBM20.5-2.0AI/ML, HPC and Data Center

Inventions

Phase Interpolator-Based CDR

Reduces cost, power and area of clock and data recovery (CDR) circuit and improves jitter performance in high-speed parallel and serial links versus PLL-based CDRs.

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