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Interface IP

HBM3 PHY

The Rambus High-Bandwidth Memory generation 3 (HBM3) PHY is optimized for systems that require a high-bandwidth, low-latency memory solution. With the integrated HBM3 Controller it comprises a complete HBM3 memory subsystem.

How the HBM3 Memory Subsystem works

HBM3 is a high-performance memory that features reduced power consumption and a small form factor. It combines 2.5D packaging with a wider interface at a lower clock speed (as compared to GDDR6) to deliver higher overall throughput at a higher bandwidth-per-watt efficiency for AI/ML and high-performance computing (HPC) applications.

The Rambus HBM3 memory subsystem supports data rates up to 8.4 Gbps per data pin. The interface features 16 independent channels, each containing 64 bits for a total data width of 1024 bits. At maximum data rate, this provides a total interface bandwidth of 1075.2 GB/s.

The interface is designed for a 2.5D system with an interposer used for routing signals between the 3D DRAM stack and the memory subsystem on the SoC. This combination of signal density and stacked form factor requires special design consideration. In order to enable easy implementation and improved flexibility of design, Rambus performs complete signal and power integrity analysis on the entire 2.5D system to ensure that all signal, power and thermal requirements are met.

HBM3 Memory Subsystem Example
HBM3 Memory Subsystem Example

The Rambus HBM3 memory subsystem supports HBM3 memory devices with 2, 4, 8, 12 and 16 DRAM stack height with densities of up 32 Gb. The subsystem maximizes bandwidth and latency via Look-Ahead command processing.

The Rambus HBM3 memory subsystem comprises an integrated HBM3 PHY and Controller. Alternatively, these cores can be licensed separately to be paired with 3rd-party HBM3 controller or PHY solutions.

HBM2E Raises the Bar for Memory Bandwidth

HBM2E Raises the Bar for Memory Bandwidth

AI/ML training capabilities are growing at a rate of 10X per year driving rapid improvements in every aspect of computing hardware and software. HBM2E memory is the ideal solution for the high bandwidth requirements of AI/ML training, but entails additional design considerations given its 2.5D architecture. Designers can realize the full benefits of HBM2E memory with the silicon-proven memory subsystem solution from Rambus.

Solution Offerings

2.5D/3D Packaging Solutions for AI and HPC

2.5D/3D Packaging Solutions for AI and HPC

For AI and HPC applications, HBM2E memory can deliver excellent bandwidth, capacity and latency in a very compact footprint thanks to its 2.5D/3D structure. The flipside is that this same structure leads to greater design complexity and raises a new set of implementation considerations.

Protocol Compatibility

ProtocolData Rate (Gbps) Application
HBM34.8, 5.6, 6.4, 8.4AI/ML, HPC, Data Center, Graphics

Inventions

Phase Interpolator-Based CDR

Reduces cost, power and area of clock and data recovery (CDR) circuit and improves jitter performance in high-speed parallel and serial links versus PLL-based CDRs.