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PCIe Switch for USB4
The PCIe Switch for USB4 (formerly XpressSWITCH) is a customizable, embedded switch for PCI Express (PCIe) designed for implementations in USB4 devices.
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Product BriefHow the PCIe Switch for USB4 Works
A fully configurable fanout switch, the PCIe Switch for USB4 provides one upstream port and up to 31 downstream ports. It enables designers to support tunneling of PCIe traffic in USB4 Hubs as mandated by the USB4 specification, and is also an ideal addition to USB4 Devices or Hosts for attaching internal or external PCIe devices.
By implementing internal PCIe devices, designers can differentiate their USB4 ICs while reducing latency and power consumption. The PCIe Switch for USB4 provides a flexible, scalable and configurable PCIe switching solution for USB4 Hubs, Hosts and Devices.
Data Center Evolution: The Leap to 64 GT/s Signaling with PCI Express 6.1
The PCI Express® (PCIe®) interface is the critical backbone that moves data at high bandwidth and low latency between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. With the rapid rise in bandwidth demands of advanced workloads such as AI/ML training, PCIe 6.1 jumps signaling to 64 GT/s with some of the biggest changes yet in the standard.
Solution Offerings
PCI Express Interfaces (upstream and downstream ports)
- Designed to the USB4 Specification v1.0
- Follows PCIe 1.0 protocol, but can operate at any compatible speed
- 1 upstream port, up to 31 downstream ports
- Supports PCIe Base Revision 5.0, backward compatible down to 3.1
- Supports PHY Interface for PCIe (PIPE) 5.x
- Single Virtual Channel (VC) implementation
- Configurable PIPE interface (8-bit, 16-bit, 32-bit, 64-bit)
- Configurable Receive and Replay buffer sizes
- Advanced Error Reporting (AER) supported on each port
- ECRC generation and check
- LTR, ACS, FPB, PTM, Hot Plug enabled per USB4 Specification mandate for Hubs
- Lane reversal supported
- Switch upstream port supports multiple physical functions
- Supports for in-the-flow processing
- ASPM L1, L2
- Clock and Power gating
- Peer-to-peer communication between downstream ports
Switching Logic
- PCIe TLP routing: Configuration, Memory Write/Read, I/O and Messages Packets
- L1 and wake-up events forwarding
- Peer-to-Peer transactions support between downstream ports
- Broadcast and Multicast supported
- Downstream Port Containment (DPC and eDPC) supported
- Round-Robin arbitration
- No Packet buffering (cut-through architecture) for reduced latency
- Built-in advanced data protection including ECRC, LCRC, ECC and Parity
- Test port available for switch logic monitoring
- Integrated Clock Domain Crossing to support user-specified frequency in the Switching logic
Unique Features & Capabilities
- Fully transparent design eliminates the need for Host configuration and management software
- Built-in support for PIPE-attached embedded endpoints (including 64-bit PIPE) for reduced BoM, latency, and power
- Seamless implementation on ASIC and FPGA with same RTL code base, up to x8 Gen4 per port on FPGA (or x16 Gen3)
- Lowest latency switching logic on the market (2 clock cycles)
- Architecture allows insertion of custom processing in-the-flow (i.e. filtering, encryption, etc.)
- The only solution that supports Hot Plug
IP files
- Verilog RTL source code
- Libraries for functional simulation
- Configuration assistant GUI
Verification Environment
Documentation
Reference Designs
- Synthesizable Verilog RTL source code
- Simulation environment and test scripts
- Synthesis project & constraint files
Advanced Design Integration Services:
- Customization of IP to add customer-specific features
- Generation of custom reference designs
- Generation of custom verification environments
- Design/architecture review and consulting
