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Interface IP

PCIe 5.0 Digital Controller

The Northwest Logic Expresso 5.0 Digital Controller is designed to achieve maximum PCI Express (PCIe) 5.0 performance with great design flexibility and ease of integration. It is fully backward compatible with PCIe 4.0, 3.0 and 2.0. With the Rambus PCIe 5.0 PHY, it forms a comprehensive interface solution delivering high-bandwidth and low-latency connectivity for next-generation applications in artificial intelligence (AI), data center, edge, 5G infrastructure and graphics.

How the PCIe 5.0 Interface Works

The Expresso 5.0 digital controller and PCIe 5.0 PHY together comprise a high-performance serial link subsystem. Optimized for challenging, performance-intensive applications, our PCIe 5.0 interface solution is ideal for AI, data center, edge, 5G infrastructure and graphics.

The Expresso 5.0 digital controller has been co-verified with the PCIe 5.0 PHY. Both PHY and controller support PCIe 5.0, 4.0, 3.0 and 2.0 protocols and are PIPE 5.1 compliant. They can be used together or paired with PIPE 5.1-compliant 3rd-party solutions.

PCIe 5.0 Interface Subsystem Example
PCIe 5.0 Interface Subsystem Example

PHY and controller are configurable in x2, x4, x8 and x16 lane configurations with bifurcation support. This gives the interface improved flexibility and support for a wide range of applications. Multi-tap transmitter and adaptive receiver equalization supports more than 36dB of channel insertion loss.

The PCIe 5 SerDes PHY is available on an advanced 7nm FinFET process node. The Expresso 5.0 controller can be synthesized on any process.

Data Center Evolution: Accelerating Computing with PCI Express 5.0

Data Center Evolution: Accelerating Computing with PCI Express 5.0

The PCI Express® (PCIe) interface is the critical backbone that moves data at high bandwidth between various compute nodes such as CPUs, GPUs, FPGAs, and workload-specific accelerators. The rise of cloud-based computing and hyperscale data centers, along with high-bandwidth applications like artificial intelligence (AI) and machine learning (ML), require the new level of performance of PCI Express 5.0. 

Solution Offerings

Protocol Compatibility

ProtocolData Rate (Gbps) Application
PCIe 2.05High-bandwidth peripherals and graphics
PCIe 3.08Servers, storage, networking devices
PCIe 4.016Servers, storage, networking devices
PCIe 5.032AI, servers, storage, networking, 5G infrastructure
SerDes Signal Integrity Challenges at 28Gbps and Beyond

SerDes Signal Integrity Challenges at 28Gbps and Beyond

Maintaining signal integrity has become increasingly difficult as data rates moves past 28Gbps to 56Gbps and beyond. Up to 28Gbps rates, NRZ is the preferred and standardized encoding scheme which consists of 1’s and 0’s. NRZ is also referred to as PAM2 (pulse amplitude modulation, 2-level), due to its two amplitude levels which contain 1 bit of information in every symbol. With serial data rates hitting 56 Gb/s per channel, signal impairments caused by increased bandwidth has prompted the high-speed serial data industry to adopt PAM4, or 4-level pulse amplitude modulation. 


Phase Interpolator-Based CDR

Reduces cost, power and area of clock and data recovery (CDR) circuit and improves jitter performance in high-speed parallel and serial links versus PLL-based CDRs.

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