Interface IP
PCIe 5.0 Digital Controller
The Northwest Logic Expresso 5.0 Digital Controller is designed to achieve maximum PCI Express (PCIe) 5.0 performance with great design flexibility and ease of integration. It is fully backward compatible with PCIe 4.0, 3.0 and 2.0. With the Rambus PCIe 5.0 PHY, it forms a comprehensive interface solution delivering high-bandwidth and low-latency connectivity for next-generation applications in artificial intelligence (AI), data center, edge, 5G infrastructure and graphics.
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Product BriefHow the PCIe 5.0 Works
The Expresso 5.0 digital controller and PCIe 5.0 PHY together comprise a high-performance serial link subsystem. Optimized for challenging, performance-intensive applications, our PCIe 5.0 interface solution is ideal for AI, data center, edge, 5G infrastructure and graphics.
The Expresso 5.0 digital controller has been co-verified with the PCIe 5.0 PHY. Both PHY and controller support PCIe 5.0, 4.0, 3.0 and 2.0 protocols and are PIPE 5.2 compliant. They can be used together or paired with PIPE 5.2-compliant 3rd-party solutions.
PHY and controller are configurable in x2, x4, x8 and x16 lane configurations with bifurcation support. This gives the interface improved flexibility and support for a wide range of applications. Multi-tap transmitter and adaptive receiver equalization supports more than 36dB of channel insertion loss.
The PCIe 5 SerDes PHY is available on an advanced 7nm FinFET process node. The Expresso 5.0 controller can be synthesized on any process.
Solution Offerings
- Complete SerDes subsystem solution with co-validated PCIe 5.0 PHY
- PIPE 5.2-compliant interface for integration with 3rd-party PHYs
- Supports PCIe 5.0, 4.0, 3.0 and 2.0
- Duplex lane configurations of x1, x2, x4, x8 and x16
- 32, 16, 8, 5 and 2.5 Gbps SerDes support
- 1-8 Physical Function support
- SR-IOV support with up to 255 Virtual Functions Endpoint, Root Port, Upstream Switch Port, Downstream Switch Port, Bifurcation support
- 32, 64, 128, 256 and 512-bit core width support
- Flexible equalization algorithms
- Full Transaction Layer (TL) Partial TL and TL Bypass interface options available
- Comprehensive diagnostics and debug status
- AER, ECRC, MSI-X, MSI, Lane Reversal support, L1 PM sub-states, SRIS, ECC/Parity Protection
- Fully validated with target PHY
- Core (source code)
- Testbench (source code)
- Complete documentation
- Expert technical support
- Maintenance updates
Engineering Design Services:
- Customization
- SoC integration
Protocol Compatibility
| Protocol | Data Rate (Gbps) | Application |
|---|---|---|
| PCIe 2.0 | 5 | High-bandwidth peripherals and graphics |
| PCIe 3.0 | 8 | Servers, storage, networking devices |
| PCIe 4.0 | 16 | Servers, storage, networking devices |
| PCIe 5.0 | 32 | AI, servers, storage, networking, 5G infrastructure |
SerDes Signal Integrity Challenges at 28Gbps and Beyond
Maintaining signal integrity has become increasingly difficult as data rates moves past 28Gbps to 56Gbps and beyond. Up to 28Gbps rates, NRZ is the preferred and standardized encoding scheme which consists of 1’s and 0’s. NRZ is also referred to as PAM2 (pulse amplitude modulation, 2-level), due to its two amplitude levels which contain 1 bit of information in every symbol. With serial data rates hitting 56 Gb/s per channel, signal impairments caused by increased bandwidth has prompted the high-speed serial data industry to adopt PAM4, or 4-level pulse amplitude modulation. For PAM4 signals, the baud rate equals one-half the bit rate and the Nyquist frequency equals one-fourth the bit rate. Compared to PAM2/NRZ, PAM4 cuts the bandwidth for a given data rate in half by transmitting two bits in each symbol. This allows engineers to double the bit rate in the channel without doubling the required bandwidth.
Inventions
Phase Interpolator-Based CDR
Reduces cost, power and area of clock and data recovery (CDR) circuit and improves jitter performance in high-speed parallel and serial links versus PLL-based CDRs.
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