Scott Best

Scott Best

Technical Director

Research Areas: Memory architectures, 3D packaging, Security processors

Scott Best joined Rambus in October 1998 who, while serving in many and varied technical roles, has become one of the most prolific inventors in the company’s history. Over the course of his career at Rambus, he is a named inventor on over 200 patents worldwide.

In his initial role with Rambus, he worked as a mixed-signal circuit designer on high-speed memory PHY projects. Those efforts culminated in 2006 with the release of the CELL microprocessor, the CPU within the PlayStation 3 gaming platform. For the next eight years, he worked in the Memory Architecture group with a focus on advanced 3D and 2.5D memory systems. This group was the genesis of the Rambus Labs team where he worked until 2014. After that, he transitioned to the then recently acquired Cryptography Research team, first in a technical role on the anti-counterfeiting product team and later as product manager for that team. His current focus is the director of anti-tamper technology development as well as business-line manager for silicon security products for U.S. Defense.

Scott holds a Bachelor of Science in Electrical Engineering from Cornell University. He is a husband, a father and skeptical technophile who lives and works in Palo Alto, California.

Rambus Inventor Profile – Scott Best
Watch Scott Best discuss Rambus advances in memory disaggregation for high performance, low power server applications.


  • B.S. Electrical Engineering from Cornell University

Research Papers

  • Power-efficient I/O design considerations for high-bandwidth applications, Custom Integrated Circuits Conference (CICC), Sept. 2011
  • Challenges and solutions for next generation main memory systems,” Electrical Performance of Electronic Packaging and Systems, Oct. 2009
  • System Co-Design and Co-Analysis Approach to Implementing the XDR Memory System of the Cell Broadband Engine Processor, Design Automation Conference, Jan. 2007

Past Speaking Engagements

  • A 256GB/s Memory Subsystem Built Using a Double-Sided IC Package with a Memory Controller and 3D-Stacked DRAM, DesignCon, Jan. 2013
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