Photo of Scott Best

Scott Best

Title: Senior Principal Engineer
Research Areas: Memory architectures, 3D packaging, Security processors

I knew from a young age that a passion for invention was part of my DNA. It started as early as 5th grade, when our class was given an advertising project – we had to develop a product and pitch it to the class. My team came up with “colored contact lenses”, which was well before they were popular and before I even knew they existed as a cosmetic product. At the time, I just thought it would be really cool to see the world in different colors each day.

Between my elementary school days and today, I’ve come to see inventing as a competitive sport. There is unquestionably a race to get the best idea on file at the patent office before your competitors do. I find this aspect of invention very compelling, as multiple groups of very talented people all across the world are trying to find the most elegant solutions to big, valuable problems.

Throughout my educational and professional life, whenever I see a big problem of an inevitable trend, I feel compelled to participate in discovering what the future will understand as the most apparent solution. I joined Rambus because of the company’s highly supportive environment for creative problem solving. And even after 15 years, I am still impressed by the ability of the talented engineers and executives to identify key technological trends that create new opportunities in high-growth markets.

Over the course of my career I’ve been a named inventor on over 60 patents, primarily in high-performance signaling and clocking solutions for DRAM and 3D memory systems. Those patents are a product of not just my work, but the collaboration of my colleagues, and the companies that have empowered me to fulfill my life-long passion of developing innovative solutions.

Watch Scott Best discuss Rambus advances in memory disaggregation for high performance, low power server applications.

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Education

  • B.S. Electrical Engineering from Cornell University

Research Papers

  • Power-efficient I/O design considerations for high-bandwidth applications, Custom Integrated Circuits Conference (CICC), Sept. 2011
  • Challenges and solutions for next generation main memory systems,” Electrical Performance of Electronic Packaging and Systems, Oct. 2009
  • System Co-Design and Co-Analysis Approach to Implementing the XDR Memory System of the Cell Broadband Engine Processor, Design Automation Conference, Jan. 2007

Past Speaking Engagements

  • A 256GB/s Memory Subsystem Built Using a Double-Sided IC Package with a Memory Controller and 3D-Stacked DRAM, DesignCon, Jan. 2013