I was drawn to Rambus to focus on cutting edge computing technologies. Throughout my 15+ year career, I’ve helped invent, create and develop means of driving and extending performance in both hardware and software solutions. At Rambus, we are solving challenges that are completely new to the industry and occur as a response to deployments that are highly sophisticated and advanced.
As an inventor, I find myself approaching a challenge like a room filled with 100,000 pieces of a puzzle where it is my job to figure out how they all go together – without knowing what it is supposed to look like in the end. For me, the job of finishing the puzzle is as enjoyable as the actual process of coming up with a new, innovative solution.
For example, RDRAM®, our first mainstream memory architecture, implemented in hundreds of millions of consumer, computing and networking products from leading electronics companies including Cisco, Dell, Hitachi, HP, Intel, etc. We did a lot of novel things that required inventiveness – we pushed the envelope and created state of the art performance without making actual changes to the infrastructure.
I’m excited about the new opportunities as computing is becoming more and more pervasive in our everyday lives. With a world full of data, my job and my fellow inventors’ job will be to stay curious, maintain an inquisitive approach and create solutions that are technologically superior and that seamlessly intertwine with our daily lives.
After an inspiring work day at Rambus, I enjoy spending time with my family, being outdoors, swimming, and reading.
- Ph.D., Electrical Engineering, Stanford University
- M.S. Electrical Engineering, Stanford University
- Master of Engineering, Harvey Mudd College
- B.S. Engineering, Harvey Mudd College
- “Prototyping a Hybrid Main Memory Using a Virtual Machine Monitor.” In Proceedings of the 2008 International Conference on Computer Design, pp 272-279: Dong Ye, Aravind Pavuluri, Carl A. Waldspurger, Brian Tsang, Bohuslav Rychlik, Steven Woo.
- “Pattern Generation Tools for the Development of Memory Core Test Patterns for Rambus Devices.” In Proceedings of the 2000 International Test Conference, pp 444-453: John Privitera, Steven Woo, and Craig Soldat.
- “The Splash-2 Programs: Characterization and Methodological Considerations.” In Proceedings of the 1995 International Symposium on Computer Architecture, pp 24-36: Steven Woo, Moriyoshi Ohara, Evan Torrie, Jaswinder Pal Singh, and Anoop Gupta.
- “The Performance Advantages of Integrating Block Data Transfer in Cache-Coherent Multiprocessors.” In Proceedings of the Sixth International Conference on Architectural Support for Programming Languages and Operating Systems, pp 219-229: Steven Woo, Jaswinder Pal Singh, and John Hennessy.
Past Speaking Engagements
- “DRAM and Memory System Trends,” Keynote speech at the 2004 International Symposium on Memory Management.
- “Challenges for Memory Systems in Future Gaming Platforms,” 2011 International Games Innovation Workshop.
- “The Evolving Landscape of Computing: Challenges for Future Memory Systems,” Rambus Design Seminar, Seoul, Korea, 2011.
- “High Performance Memory System Challenges,” 21st Annual Workshop on Interconnections within High Speed Digital Systems, 2010.
- “Meeting the Challenges for Next-Generation Mobile and Graphics Memory,” Intel Developer Forum 2010.
- “Memory System Challenges in the Multi-Core Era,” Memcon 2008.
- “Memory System Challenges in the Multi-Core Era,” Nikkei Symposium 2008.
- “Computing Trends and Applications Driving Memory Performance,” Rambus Developer Forum, Tokyo, Japan, 2007.