With short design windows and heightened sensitivity to costs, consumer electronics need low-risk solutions that deliver enhanced flexibility and reduced time-to-market. Designed for ease-of-integration and optimized for consumer applications, our silicon-proven DDR3 PHY delivers improved performance and margin with support for low cost packaging and board design options.
The Rambus DDR3 memory PHY is optimized for consumer applications with reduced system cost, improved performance and faster time-to-market. Fully compatible with DDR3 at 1.5V and DDR3L at 1.35V and scalable to 2133Mbps, the PHY has undergone extensive design-phase modeling and simulation of alternative SOC, package and PCB environments to ease implementation and enable first-time-right designs. In order to deliver improved flexibility of design, the R+ DDR3 PHY supports wire-bond (running up to 1600 Mbps) and flip-chip (running up to 2133 Mbps) packaging options and is compatible with 4- and 6-layer PCB designs. In addition, it features FlexPhase™ circuits that enable Per byte timing adjustment circuits deskew data and clock signals to improve signal integrity and simplify package and PCB system design.
The DDR3 PHY is fully characterized and is available in 28LP process.
DDR3 Subsystem Example
Comprehensive Chip and System Design Reviews
Engineering Design Services:
|Protocol||Data Rate (Gbps)||Application|
|DDR3 (1.5V)||1600-2133||Consumer Electronics|
|DDR3L (1.35V)||1600-1866||Consumer Electronics|
ODT calibration enables higher data rates and superior DRAM device and module performance by establishing the optimal termination value to compensate for variations in process and operating conditions that degrade signal performance.