Memory + Interfaces

DDR3 Isolation Memory Buffer

Designed for power, performance and capacity optimized servers, the DDR3 Isolation Memory Buffer, recently acquired from Inphi, is a JEDEC standard chip for DDR3 LRDIMMs.


Solution Overview

How the DDR3 LRDIMM Memory Buffer works

The Load Reduced DIMM (LRDIMM) Memory Buffer (MB), iMB02-GS02B, recently acquired from Inphi, supports DDR3 SDRAM main memory. The Memory Buffer allows buffering of memory traffic to support large memory capacities. Unlike DDR3 Register Buffer (INSSTE32882), which only buffers Command, Address, Control and Clock, the LRDIMM Memory Buffer also buffers the Data (DQ) interface between the Memory Controller and the DRAM components. As the data electrical load is reduced for the Memory Controller interface, the system can now support more DIMMs per channel at a faster speed and higher density. All memory control for the DRAM resides in the host, including memory request initiation, timing, scrubbing, sparing, and power management. The Memory Buffer interface is responsible for memory requests to and from the local DIMM.

LRDIMM provides a high memory bandwidth, large capacity channel solution for DDR3 main memory systems. LRDIMM uses commodity DRAMs isolated from the channel behind the Memory Buffer on the DIMM. The supported capacity exceeds 144 devices per channel (depends on channel and individual system design) and total memory capacity scales with DRAM bit density.

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