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Memory Interface Chips

DDR3 Isolation Memory Buffer

Designed for power, performance and capacity optimized servers, the DDR3 Isolation Memory Buffer, recently acquired from Inphi, is a JEDEC standard chip for DDR3 LRDIMMs.

How the DDR3 LRDIMM Memory Buffer works

The Load Reduced DIMM (LRDIMM) Memory Buffer (MB), iMB02-GS02B, recently acquired from Inphi, supports DDR3 SDRAM main memory. The Memory Buffer allows buffering of memory traffic to support large memory capacities. Unlike DDR3 Register Buffer (INSSTE32882), which only buffers Command, Address, Control and Clock, the LRDIMM Memory Buffer also buffers the Data (DQ) interface between the Memory Controller and the DRAM components. As the data electrical load is reduced for the Memory Controller interface, the system can now support more DIMMs per channel at a faster speed and higher density. All memory control for the DRAM resides in the host, including memory request initiation, timing, scrubbing, sparing, and power management. The Memory Buffer interface is responsible for memory requests to and from the local DIMM.

LRDIMM provides a high memory bandwidth, large capacity channel solution for DDR3 main memory systems. LRDIMM uses commodity DRAMs isolated from the channel behind the Memory Buffer on the DIMM. The supported capacity exceeds 144 devices per channel (depends on channel and individual system design) and total memory capacity scales with DRAM bit density.

Solution Offerings

  • JEDEC standard footprint
  • Higher system memory bandwidth at DDR3 speeds up to 1866 MT/s. This is accomplished by isolating the Host memory controller data, control and clock signal drivers from the DRAM components on Load-Reduced DIMM (LRDIMM)
  • The iMB02-GS02B meets all JEDEC specifications for LRDIMM Memory Buffer operation up to DDR3-1866 and DDR3L-1600
  • The iMB02-GS02BL meets all JEDEC specifications for LRDIMM Memory Buffer operation up to DDR3-1600 and DDR3L-1600.
  • Higher capacity by using rank multiplication: 2, 4 and 8 ranks supported on the iMBTM and DRAM interface
  • No board change required on the current and upcoming DDR3 server systems as LRDIMM is compatible with the existing DDR3 connector interface
  • Programmable configuration interface compliant with the JEDEC 882 control word definition
  • Power optimization using improved power management control
  • Improved clock specifications using integrated PLL and clock distribution buffers from a differential clock input to four differential clock outputs configurable for skew and drive strength output control
  • Skew optimization on data groups and corresponding strobe signals for improved margins on the Host and DRAM interface. 72-bit bi-directional data buffers are matched with 18-bit differential bi-directional DQS buffers
  • Highly efficient thermal management using a JEDEC-defined flip-chip BGA package. Improved signal integrity using duplicate copies of Command and Address outputs
  • Available in 588-Ball FBGA Eco-Friendly RoHS Compliant Package (20 x 38 Array, 25.2 mm x 13.5 mm Body Size, 0.65 mm Pitch, MO-301A Variation A)
  • High-capacity virtualized servers for enterprise applications
  • Power, performance and capacity optimized servers for data centers
  • High-performance computing systems, (e.g., FAE, O&G and defense laboratories)
  • High-performance workstations for visualization and graphics intensive applications
  • Cost-effective servers in the small-medium business segment

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