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Memory Interface Chips

DDR3 Register Clock Driver

Designed for enterprise and data center systems, our DDR3 Register Clock Driver (RCD), recently acquired from Inphi, is a critical component for RDIMMs and, when combined with our DDR3 Data Buffer, LRDIMMs.

How the DDR3 Register Clock Driver works

The INSSTE32882XV-GS02 is a DDR3 registering clock driver for high-performance servers, workstations and high reliability networking and telecom systems. Designed to help meet the critical challenge of reducing energy consumption in next generation data centers, it provides high-speed timing accuracy at low power consumption. In addition, the register’s architecture is designed to deliver the industry’s lowest and most stable dynamic phase offset (tDYNOFF) and jitter specifications, helping to ensure that server platforms have adequate margins across all operating conditions, frequency and density.

The INSSTE32882XV-GS02 register supports Double Data Rate (DDR3) operation at speeds of up to
2133 MT/s and at 1.5V, 1.35V and 1.25V operation, targeting server architectures. The INSSTE32882XV-GS02 register also incorporates JEDEC-standard register features such as 1.25V operation and external Voltage Reference (VREF) margining options.

The INSSTE32882XV-GS02’s innovative combination of circuit design and process technology enables operation with minimal idle power dissipation and core current consumption. In high-end systems with 12 to 18 memory modules per server, this translates to a substantial savings in power and cost. The INSSTE32882XV-GS02 supports JEDEC-standard external reference voltage margining mode, allowing system implementers to easily sweep a memory module’s voltage operating headroom for robust system margins.

High Speed Memory Interface Chipsets Let Server Performance Fly

High Speed Memory Interface Chipsets Let Server Performance Fly

The demands on server performance continue to increase at a tremendous pace. New requirements from large in-memory databases that are powering today’s cloud services and advanced analytics tools are arriving just as the impact of Moore’s Law is starting to slow. One key new opportunity is for high-speed server memory interface chipsets, which enable high-speed memory performance without compromising on memory capacities. Companies looking to optimize their server memory architecture designs, and improve their overall server performance and reliability, should give serious consideration to optimized DDR4 memory interface chipsets, which enhance the performance of server memory modules.

Solution Offerings

  • Industry’s lowest power DDR3 register for memory module applications
  • Single Register Quad Rank RDIMM support
  • Meets or exceeds all JESD82-29 performance specifications for DDR3(L)-800/1066/1333/1600/1866 and DDR3-2133 rates
  • Operational up to 2133 MT/s at 1.5V, 1866 MT/s at 1.35V, and 1600 MT/s at 1.25V. (Specifications highlighted in blue exceed JEDEC standards.)
  • Meets or exceeds all JESD82-29 performance specifications at 1.5V and 1.35V
  • Meets or exceeds all JESD82-29 performance specifications at 1.25V
  • Exceeds JEDEC re-driven dynamic clock offset specification (tDYNOFF)
  • Exceeds JEDEC jitter requirements
  • Supports external VREF margin option
  • Supports all JEDEC lower power modes including weak-drive mode
  • ESD protection exceeds JESD22
    • HBM – 3000V
    • CDM – 800V
    • MM – 250V
  • Latch-up exceeds JESD78 class 2
  • Backward compatible with DDR3 and DDR3L RDIMM modules
  • Supports custom RDIMM modules via programmable driver characteristics
  • Available in 176 TFBGA Eco-Friendly “Green” Package (8.00 mm x 13.50 mm (MO-246F))
  • Mid and High Performance Servers
  • High Performance Workstations
  • High Reliability & Telecom Systems