Memory + Interfaces

DDR4 Data Buffer

Our DDR4 Data Buffer, recently acquired from Inphi, is built to deliver robust performance for real-time, memory-intensive applications, delivering leading I/O performance and margin. Compatible with DDR4 LRDIMMs, the Data Buffer is ideal for high-performance, high-capacity enterprise and data center systems.

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Solution Overview

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How the DDR4 Data Buffer works

Increased memory capacity and performance are critical to solving today’s complex problems with huge data sets and accelerating Big Data applications.

When combined with our DDR4 Register Clock Driver (RCD), iDDR4RCD-GS02, our DDR4 Data Buffer (DB), iDDR4DB2-GS02, recently acquired from Inphi, enables DDR4 Load Reduced Dual Inline Memory Modules (LRDIMMs) to deliver high-bandwidth performance with twice the capacity of DDR4 Registered DIMMs (RDIMMs). Designed to meet the demanding requirements for real-time, memory-intensive applications, the DB delivers enhanced performance and margin at 2400 Mbps with built-in support for future data rates up to 2666 Mbps.  This enables the highest speeds and robust operation when multiple LRDIMMs populate the memory channel for the highest system capacities.

The iDDR4DB2-GS02 dual 4-bit bidirectional data register with differential strobes is designed for 1.2 V VDD operation. The device has a dual 4-bit host bus interface that is connected to a memory controller and a dual 4-bit DRAM interface that is connected to two x4 DRAMs. It also has an input-only control bus interface that is connected to a DDR4 Register. This interface consists of a 4-bit control bus, two dedicated control signals, a voltage reference input and a differential clock input.

All DQ inputs are pseudo-differential with an internal voltage reference. All DQ outputs are VDD terminated drivers optimized to drive single or dual terminated traces in DDR4 LRDIMM applications. The differential DQS strobes are used to sample the DQ inputs and are regenerated in the DDR4 DB for driving out the DQ outputs on the opposite side of the device.

The clock inputs BCK_t and BCK_c are used to sample the control inputs BCOM[3:0], BCKE and BODT. The BCOM[3:0] inputs are used to write device internal control registers.

The iDDR4DB2-GS02 also supports dedicated pins for ZQ calibration and for parity error alerts.

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