The iDDR4RCD-GS02 32-bit 1:2 registering clock driver with parity is designed for 1.2 V VDD operation.
All inputs are pseudo-differential with an external or internal voltage reference. All outputs are full swing CMOS drivers optimized to drive single terminated 25 to 50 ohms traces in DDR4/DDR4L RDIMM and LRDIMM applications. The clock outputs Yn_t and Yn_c and control net outputs QxCKEn, QxCSn and QxODTn can be driven with different strengths to compensate for different DIMM net topologies. By disabling unused outputs the power consumption can be reduced.
The iDDR4RCD-GS02 register operates from a differential clock (CK_t and CK_c). Inputs are registered at the crossing of CK_t going HIGH, and CK_c going LOW. The input signals can be either re-driven to the outputs or they can be used to access device internal control registers when certain input conditions are met.