At Rambus, we create cutting-edge semiconductor and IP products, spanning memory and interfaces to security, smart sensors and lighting.
Rambus PMICs for client memory modules enable a broad range of form factors, performance and capacity configurations. The PMIC5120 supports DDR5 SODIMMs, CSODIMMs, UDIMMs and CUDIMMs. The PMIC5200 supports LPCAMM2, the new compression-attach memory module form factor for LPDDR5.
| Description | Part Number | Product Brief | Applications |
|---|---|---|---|
| PMIC5120 Power Management IC | P2535Gxx |  |
Client DDR5 SODIMM, CSODIMM, UDIMM, CUDIMM |
| PMIC5200 Power Management IC | P2745XXGxxxx | |
Client LPCAMM2 |
How Client Memory Module PMICs Work
In order to deliver higher levels of performance at high reliability and within the desired power envelope, DDR5 implements a number of memory module architecture changes vs. previous generation DDR4. One of these changes is to move the power management ICs from the motherboard to the individual DDR5 memory modules.
The DDR5 on-module PMIC5120 receives a single input voltage (4.25-5.5V) and generates the distinct voltage levels needed by the DRAM and other active components on the DIMM. This saves motherboard real estate and eliminates the need for motherboard voltage regulators that must be designed for the fully-populated memory module use case.
With PMICs on the DDR5 DIMMs, power management is added on an incremental basis that scales with the number of memory modules needed by the system configuration. Another advantage of this power architecture is that it greatly reduces the problem of IR drop on the delivery network by delivering the high voltage supply to the module, as opposed to trying to deliver 1V from the motherboard, through the module connector and onto the memory module. This provides tighter voltage tolerances for the sensitive components on the DIMM, which helps achieve the higher DDR5 performance level targets.
LPCAMM2, the innovative new compression-attached memory module, adopts a similar architecture in that the PMIC is implemented on the module. The LPCAMM2 PMIC5200 receives a single input voltage (3.0-5.0V) and generates all the distinct voltage levels needed to power the LPDDR5 DRAM and all other active components on the module.
PMIC5120 Features
- VIN_Bulk input supply range: 4.25 V to 5.5 V
- Operational from -10 to +125 C
- Three step-down switching regulators and two LDOs
- Programmable dual-phase and single-phase regulator for SWA and SWB
- Secure mode and programmable mode of operation
- Error injection capability
- Persistent error log registers
- Independently programmable output voltages, power up and power down sequence for switch regulators
- Output power good status reporting mechanism
- VIN_Bulk input supply protection feature: Input over voltage
- Output switch regulators protection features: Output over voltage, output under voltage, output current limiter
- Output current and power measurement, output current threshold mechanism
- Temperature measurement, temperature warning threshold, critical temperature shutdown
- Multi Time Programmable (MTP) Non-Volatile Memory
- Programmable and DIMM specific registers for customization
- Flexible Open Drain IO (I2C) and Push Pull (I3C Basic) IO support
- Parity error check and packet error check (PEC) function
- In-band Interrupt (IBI) support
- Dynamic driver switching capability for I3C Basic bus operation between push-pull and open-drain
- Flexible mechanism to enable switch regulators (w/ VR_EN pin or VR Enable command on I2C or I3C Basic interface)
- Idle Power State (P1 State)
- General Status Interrupt (GSI) function
- PMIC warranty status bit
- Fine resolution ADC (31.25mA/mW step size)
- FCQFN package: 3mm x 4mm footprint
PMIC5200 Features
- I2C and I3C basic bus serial interface support
- Meets or exceeds all JESD300-5 performance specifications up to 1MHz for I2C and 12.5MHz for I3C Basic bus serial interface
- Parity error check and packet error check (PEC) function
- In-band Interrupt (IBI) support
- VIN_Bulk input operational at 3.0V to 5.5V
- Operational from -100C to +1250C
- Four step-down switching regulators and two LDOs
- Secure mode and programmable mode of operation
- I2C bus operational at 1.0V to 3.3V nominal I/O levels
- I3C Basic bus operational at 1.0V, 1.1V, and 1.2V nominal I/O levels
- Dynamic driver switching capability for I3C Basic bus operation between push-pull and open-drain
- Flexible mechanism to enable switch regulators (w/ VR_EN pin or VR Enable command on I2C or I3C Basic interface or Auto Power On)
- Idle Power State (P1 State)
- Dynamic Voltage Frequency Scaling VDDQ (DVFSQ) function for SWB with DVFSQ_n pin
- Unlock pin for unlocked, locked and configurable lock operation
- SWB Disable Override function
- PMIC warranty status bit
- Fine resolution ADC (31.25mA/mW step size)
- 35-pin FCQFN package: 5mm x 5mm footprint
Ask the Experts: Client Memory Interface Chipsets
In this episode of Ask the Experts, we discuss client chipsets for DIMMs and LPCAMM2 with Carlos Weissenberg, Senior Product Marketing Manager, Memory Interface Chips at Rambus. Topics include: the need for advanced chips to enable higher levels of performance, the role of Client Clock Driver (CKD) and Power Management ICs (PMIC), and how AI applications are driving the need for greater memory bandwidth and capacity.
Data Center Evolution: DDR5 DIMMs Advance Server Performance
Driven by a confluence of megatrends, global data traffic is increasing at an exponential rate. For example, 5G networks are enabling billions of AI-powered IoT devices untethered from wired networks. Nowhere is the impact of all this growth being felt more intensely than in data centers. Indeed, hyperscale data centers have become the critical hubs of the global data network. DDR5 DRAM will enable the next generation of server systems providing the massive computing power of hyperscale and enterprise data centers. Learn about the benefits of DDR5 memory and the design considerations for implementing DDR5 DIMMs.
