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Rambus’ HBM2E Memory Controller & PHY Offer Chipmakers Cost-Effective Designs


The latest generation of high-bandwidth memory, HBM2E, is around the corner. Now that Samsung has started mass production of its HBM2E memory stacks, Rambus has unveiled its controller and PHY (physical interface) designs.

Rambus Develops HBM2E Controller & PHY: 3.2 Gbps, 1024-Bit Bus


The latest enhancements to the HBM2 standard will clearly be appreciated by developers of memory bandwidth-hungry ASICs, however in order to add support of HBM2E to their designs, they are also going to need an appropriate controller as well as physical interface. For many companies developing of such IP in-house does not make financial sense, so […]

Memory For Advanced Designs


The 2020 Designcon conference included many talks and exhibits with a storage and memory focus.  Both Rambus and Teledyne LeCroy had tutorials on design and connectivity for leading edge electronic components and systems as well as testing memory systems.  This piece will look at some material from the tutorials and exhibits that can inform us about disaggregated […]

Hardware Attack Surface Widening


An expanding attack surface in hardware, coupled with increasing complexity inside and outside of chips, is making it far more difficult to secure systems against a variety of new and existing types of attacks. Security experts have been warning about the growing threat for some time, but it is being made worse by the need […]

Rambus Reports Fourth Quarter and Fiscal Year 2019 Financial Results


Excellent quarter, exceeding expectations; GAAP revenue of $59.9 million; with licensing billings of $63.8 million, product revenue of $26.6 million, and contract and other revenue of $13.9 million Record Q4 and full-year revenue for both the Memory Interface Chips and Silicon IP businesses $35.4 million in cash provided by operating activities in Q4 and $128.5 […]

Securing our IoT future


The holiday season brought with it a surge of new IoT devices, from smart toys and doorbells to automatic pet feeders – and it doesn’t stop there. According to IDC, investment in IoT is predicted to top $1 trillion in 2020. As our homes, businesses and cities become more connected than ever before, this number […]

Storage and Networking Bytes: PCIe5, OpenShift, and Veeam


Let’s start with PCIe5, the spec for which was finalized in early 2019. Now manufacturers are now getting revved up to produce PCIe5 hardware in 2020, which will be a boon for data- and processor-hungry workloads like machine learning and AI, as well as high performance computing (HPC) workloads that rely on GPUS, FPGAs, and […]

Accelerating AI And ML Applications With PCIe 5


The rapid adoption of sophisticated artificial intelligence/machine learning (AI/ML) applications and the shift to cloud-based workloads has significantly increased network traffic in recent years. Historically, the intensive use of virtualization ensured that server compute capacity adequately met the need of heavy workloads. This was achieved by dividing or partitioning a single (physical) server into multiple […]

What Makes Secure Processors Different?


Given the magnificent complexity of modern microprocessors, it’s inevitable that they’ll have bugs and security holes. It might even be physically impossible to create a bug-free CPU, but that’s a mathematics/physics/EDA/statistics/philosophical conundrum that’s above my paygrade. For now, we finds the bugs and we works around ’em.

Memory subsystem solution for next-generation AI training chip


Rambus has announced that Enflame (Suiyuan) Technology has selected Rambus HBM2 PHY and Memory Controller IP for its next-generation AI training chip. Rambus memory interface IP enables the development of high-performance, next-generation hardware for leading-edge AI applications.

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