In 1945, mathematician and physicist John von Neumann described a design architecture for an electronic digital computer in the First Draft of a Report on the EDVAC. Also known as the Princeton architecture, the design included a processing unit with an arithmetic logic unit and processor registers; a control unit containing an instruction register and program counter; memory to store both data and instructions; external mass storage; as well as an input and output mechanism.
Emerging Solutions
Rambus inks license agreement with Xilinx
Rambus has signed a license agreement with Xilinx that covers Rambus’ patented memory controller, SerDes and security technologies.
In addition, the two companies have agreed to evaluate potential collaboration on the use of Rambus’ CryptoManager platform, with Rambus also exploring the use of Xilinx FPGAs in its Smart Data Acceleration (SDA) research program.
Video: Evaluating Lensless Smart Sensors (POD 2.0)
Lensless Smart Sensor (LSS) technology is helping to enable a new generation of low-power sensing by capturing information-rich images with a low-cost phase grating, standard image sensors and sophisticated computational algorithms. To accelerate LSS adoption and further explore additional use cases, Rambus has released its POD 2.0 evaluation system for LSS technology.
Eyeing the future of smart cities
Rambus principal research scientist Patrick Gill recently penned an article for Telecoms Tech about how lensless smart sensors (LSS) can potentially play an important role in building future smart cities. As Gill notes, LSS technology offers a fundamentally new approach to visual sensing by shifting the function of traditional optics to computation, thereby eliminating the need for expensive lenses by replacing them with tiny, inexpensive diffractive gratings.
The role of FPGA acceleration in the data center and beyond
The International Conference on Field-Programmable Logic and Applications recently convened in Lausanne, Switzerland. As Christoforos Kachris, a senior researcher at the National Technical University of Athens notes, exploring the role of FPGAs in the data center took center stage at the conference.
“Christoph Hagleitne presented IBM’s view of the major applications where FPGAs can provide differentiation such as cognitive computing, high performance computing and the Internet of Things (IoT),” Kachris wrote in a recent EE Times article.
Accelerating high performance computing systems
Esthela Gallardo and Patricia J. Teller recently penned an article for HPC Wire that explores the various challenges associated with cross-accelerator performance profiling. As Gallardo and Teller note, high performance computing (HPC) systems are comprised of multiple compute nodes interconnected by a network.
“Previously these nodes were composed solely of multi-core processors, but nowadays they also include many-core processors, which are called accelerators,” the authors explained.