Writing for Semiconductor Engineering, Ernest Worthman notes that while stacked die may improve performance and lower power, the use of through-silicon vias (TSVs) could potentially add new security risks. “With 2.5D architectures, IP blocks can be designed on separate dies and assembled using an interposer. Such a chip can have a stacked DRAM, a Wi-Fi radio and flash memory, together with the processor in a single package,” Worthman explained.
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On-chip Noise Monitor accelerates time-to-market for complex SOCs
Rambus has added an On-chip Noise Monitor to its suite of tools and IP cores. According to Loren Shalinsky, a Strategic Development Director at Rambus, the Noise Monitor is designed to accurately characterize power supply noise of low- power, high-performance complex IPs and electronic systems.
Xiaomi’s Mi Note Pro is loaded with 4GB of RAM
Announced earlier this month at CES 2015, the Asus Zenfone 2 features a 64-bit Intel Atom Z3580 processor and supports up to 4GB LPDDR3 DRAM. As we previously confirmed on Rambus Press, the Zenfone 2 was the very first smartphone to carry a full payload of 4GB of RAM. Unsurprisingly, a number of manufacturers are eyeing 4GB of RAM for their next-gen smartphones and phablets.
DRAM vendors top semiconductor industry
Worldwide semiconductor revenue reportedly totaled $339.8 billion in 2014, marking a 7.9 percent increase from $315 billion in 2013. According to Gartner, the top 25 semiconductor vendors’ combined revenue increased 11.7 percent, which was more than the overall industry’s growth. More specifically, the top 25 vendors accounted for 72.1 percent of total market revenue, up from 69.7 percent in 2013.
Rambus to take center stage at DesignCon 2015
DesignCon 2015 kicks off January 27th in Santa Clara, California, where Rambus will be showcasing a wide range of R+ enhanced standard memory and serial IP core solutions. So be sure to stop by booth #835, where you can learn about multi-modal functionality, low-power signaling modes, per-bit FlexPhase timing adjustment capabilities, enhanced in-PHY testability and wider integration with LabStation™ Validation Platform.
The 2025 security UX
It’s a chilly, overcast winter day in Seattle. Freezing rain drizzles from trademark gray skies, pattering gently against the glass windows of a local coffee shop. Sitting alone at a dimly lit table, Mia takes one last sip of espresso from a worn, chipped mug before donning her glasses and jacking into a Virtual Security Dock (VSD).
