With the publishing of the HBM3 update to the High Bandwidth Memory (HBM) standard, a new king of bandwidth is crowned. The torrid performance demands of advanced workloads, with AI/ML training leading the pack, drive the need for ever faster delivery of bits. Memory bandwidth is a critical enabler of computing performance, thus the need for the accelerated evolution of the standard with HBM3 representing the new benchmark.
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Building A Defense In Depth Against Cyberattacks
As the number and type of cyberattacks, from the “simple and cheap” to the “expensive and sophisticated,” continues to grow at a dramatic pace, protection of chips and devices must employ a defense in depth strategy. In this way, if an attacker successfully bypasses a mechanism of protection, they’ll face another layer of defense, rather than a clear path to the assets they seek to exploit. In this blog, we’ll talk about some of the protections security architects can marshal to build a defense in depth.
Power Grids Under Attack
Cyberattacks are becoming as troublesome to the electrical power grid as natural disasters, and the problem is growing worse as these grids become more connected and smarter. Unlike in the past, when a power outage affected just the electricity supplied to homes and businesses, power grids are becoming core elements of smart cities, infrastructure, and safety-related services. Without power, none of this works, and sophisticated cybercriminal operations can hold large regions hostage until they pay enormous ransoms or give into other demands.
CXL™ Consortium Member Spotlight: Rambus
CXL™ Consortium member company Rambus participated in a recent Q&A session to discuss CXL’s impact on the evolution of the data center, Rambus’ expertise in CXL interface subsystems, and ideal use cases for CXL technology. Find the full Q&A session with Rambus below.
Avery Design Systems and Rambus Extend Memory Model and PCIe® VIP Collaboration
Tewksbury, MA. and San Jose, Calif. – May 19, 2021 – Avery Design Systems, a leader in functional verification solutions, and Rambus Inc. (NASDAQ: RMBS), a provider of industry-leading chips and silicon IP making data faster and safer, announced today they are extending their long-term memory model and PCIe® Verification IP (VIP) collaboration.
Rambus utilizes Avery’s high-quality, full-featured memory models to verify their memory controllers including HBM2/2E, GDDR6, LPDDR4, and DDR3/4. Rambus includes these memory models in its customer deliveries to enable out-of-the-box simulations with the delivered IP. Customers can then license the Avery memory models for use in full SoC verification. Rambus utilizes Avery’s PCIe VIP to verify its PCIe 5.0/4.0 controllers, including Endpoint, Root Port and Retimer modes, and PHYs.
“Avery’s cutting-edge VIP has enabled Rambus to verify controllers which support the most advanced features needed by customers in their current and next-generation designs,” said Brian Daellenbach, senior director of Digital Controllers, IP Cores at Rambus. “The collaboration between Avery and Rambus has helped both companies offer fully-verified IP solutions addressing the latest market requirements.”
“Rambus and Avery are both focused on creating best-in-class, robust, pre-validated memory and PCIe IP solutions which streamline the design and verification process for our customers. We look forward to continuing our collaboration to address the current and next-generation protocols being used by the market,” said Chris Browy, vice president sales/marketing of Avery.
About Avery Design Systems
Founded in 1999, Avery Design Systems, Inc. enables system and SOC design teams to achieve dramatic functional verification productivity improvements through the use of formal analysis applications for gate-level X-pessimism verification and real X root cause and sequential backtracing; and robust core-through-chip-level Verification IP for PCI Express, CXL, CCIX, Gen-Z, USB, AMBA, UFS, MIPI CSI/DSI, I3C, DDR/LPDDR, HBM, ONFI/Toggle/NOR, NVM Express, SATA, AHCI, SAS, eMMC, SD/SDIO, CAN FD, and FlexRay standards. The company has established numerous Avery Design VIP partner program affiliations with leading IP suppliers. More information about the company may be found at www.avery-design.com.
Compute Express Link and CXL are trademarks of the CXL Consortium
PCI Express and PCIe® are trademarks of PCI-SIG
AI Drives Memory Interconnect Evolution
TORONTO — Location, location, location is not a mantra limited to real estate. To meet the needs of artificial intelligence (AI) and machine learning applications, it increasingly applies to where data needs to reside, and the memory that stores it.
