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Joseph Rodriguez, senior product marketing engineer for IP cores at Rambus, has written an article for Semiconductor Engineering that explores the company’s recent achievement of reaching 4 gigabits per second (Gbps) data rate with its HBM2E memory interface. The milestone – which was demonstrated in silicon – required mastering substantial signal integrity and power integrity […]
CXL Memory Initiative Enabling new memory tiers for breakthrough server performance Contact Us Data Center Challenges Data centers face three major memory challenges as roadblocks to greater performance and total cost of ownership (TCO). Data Center Memory Challenges The first of these is the limitations of the current server memory hierarchy. There is a three […]
Tewksbury, MA. and San Jose, Calif. – May 19, 2021 – Avery Design Systems, a leader in functional verification solutions, and Rambus Inc. (NASDAQ: RMBS), a provider of industry-leading chips and silicon IP making data faster and safer, announced today they are extending their long-term memory model and PCIe® Verification IP (VIP) collaboration. Rambus utilizes Avery’s high-quality, full-featured memory models to verify their memory […]
Frank Ferro, Senior Director Product Management at Rambus, recently penned an article for Semiconductor Engineering that takes a closer look at high bandwidth memory (HBM) and 2.5D (stacking) architecture for AI/ML training. As Ferro notes, the impact of AI/ML increases daily – impacting nearly every industry across the globe. “In marketing, healthcare, retail, transportation, manufacturing […]
Artificial Intelligence/Machine Learning (AI/ML) grows at a blistering pace. The size of the largest training models has passed 100 billion parameters and is on pace to hit a trillion in the next year. The impact of AI/ML is being felt across the industry landscape, in higher education, and in financial markets. Underpinning this growth is […]
Highlights: Supports accelerators requiring terabyte-scale bandwidth for artificial intelligence/machine learning (AI/ML) training applications Fully-integrated HBM2E memory interface subsystem, consisting of verified PHY and controller, silicon proven on advanced Samsung 14/11nm FinFET process Backed by unrivaled system expertise supporting customers with interposer and package reference designs to speed time to market SAN JOSE, Calif. – April 21, 2021 – Rambus […]
Highlights: Agreement makes Rambus Root of Trust, Secure Protocol Engines, along with Memory and SerDes PHYs and Controllers available to DARPA researchers Streamlined access to cutting-edge silicon IP accelerates forward-looking innovation DARPA researchers will be able to leverage industry-leading capabilities and expertise from Rambus SAN JOSE, Calif. – April 14, 2021 – Rambus Inc. (NASDAQ: RMBS), a provider of […]
Frank Ferro, Senior Director Product Management at Rambus, has written a detailed article for Semiconductor Engineering that explains why HBM2E is a perfect fit for Artificial Intelligence/Machine Learning (AI/ML) training. As Ferro points out, AI/ML growth and development are proceeding at a lighting pace. Indeed, AI training capabilities have jumped by a factor of 300,000 […]
Rambus Tech Days April 19 – 21, 2021 Register Today Rambus Tech Days are three afternoons of deep dive technical presentations covering topics from MACsec to MIPI. Join security and interface technology leaders from Rambus and its partners as they discuss the latest solutions for safeguarding and accelerating data in applications spanning AI/ML, data center, […]
As a momentous 2020 fades into the history books, 2021 is expected to be a year of growth and evolution for the semiconductor industry across multiple market segments. Firstly, DDR5 DRAM is slated to enter volume production by the end of 2021, with initial deployments targeting hyperscale data centers. Secondly, AI/ML neural networks – which […]