At Rambus, we create cutting-edge semiconductor and IP products, providing industry-leading chips and silicon IP to make data faster and safer.
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SEAKR Selects Rambus SerDes and Security IP for Aerospace and Satellite Communications
https://www.rambus.com/seakr-selects-rambus-serdes-and-security-ip-for-aerospace-and-satellite-communications/Highlights: SEAKR chooses Rambus 28G Multi-protocol long reach (LR) SerDes PHY and CryptoManager Root of Trust for aerospace and satellite communications Combined SerDes and Security IP portfolio offers a one-stop-shop for chip designers, making data faster and safer Silicon-proven technologies help enable faster, more secure, mission-critical aerospace electronic systems SUNNYVALE, CA, and CENTENNIAL, CO – […]
Rambus’ Ben Levine talks IoT security and cryptography with EDA Café
https://www.rambus.com/blogs/rambus-ben-levine-talks-iot-security-and-cryptography-with-eda-cafe-2/Ben Levine, Senior Director of Product Marketing at Rambus, recently sat down with Sanjay Gangal of EDA Café to discuss IoT security and cryptography. According to Levine, security should be embedded in every chip. More specifically, says Levine, a separate hardware-based security core can help protect both the SoC itself and the system it powers. […]
Optimizing Memory for AI Applications: Part 2
https://www.rambus.com/blogs/optimizing-memory-for-ai-applications-part-2/In part one of this two-part blog series, Steven Woo, Rambus fellow and distinguished inventor, spoke with Ed Sperling of Semiconductor Engineering about utilizing various number formats to optimize memory bandwidth for artificial intelligence (AI) applications. In this blog post, we’ll be taking a closer look at the impact specific number formats have on performance […]
Optimizing Memory for AI Applications: Part 1
https://www.rambus.com/blogs/optimizing-memory-for-ai-applications-part-1/Steven Woo, Rambus fellow and distinguished inventor, recently spoke with Ed Sperling of Semiconductor Engineering about how certain number formats can help system designers optimize memory bandwidth for artificial intelligence (AI) applications. As Woo observes, such optimization is necessary because the semiconductor industry is constantly struggling to keep up with an exponential increase of digital […]
Rambus Tapes Out 112G XSR SerDes PHY on Leading-edge 7nm Process
https://www.rambus.com/rambus-tapes-out-112g-xsr-serdes-phy/Highlights: Provides critical building block to deliver data for next-generation data center, networking, high-performance computing (HPC), artificial intelligence (AI) and machine learning (ML) applications Delivers superior power, performance and area (PPA) for extra short reach (XSR) links with innovative architecture designed for leading-edge 7nm process node Expands SerDes PHY portfolio for 112G OIF-CEI industry standard […]
Chiplets keep the scaling of integrated circuits (ICs) rolling
https://www.rambus.com/blogs/chiplets-keep-the-scaling-of-integrated-circuits-ics-rolling/As data grows at an accelerating pace, more compute power and bandwidth are required to process this data, driving the need for larger and more complex system on chips (SoCs). This is particularly true at a time when our old friend Moore’s Law has lost a step. However, as the complexity of SOCs increases, so […]
Secure Boot
https://www.rambus.com/security/software-protocols/secure-boot/Secure Boot Contact Us The Rambus Secure Boot solution (formerly from Inside Secure) provides tools for integrating security into an embedded device’s system boot sequence. The Secure Boot solution uses strong cryptography to protect the boot process of SoCs and application processors. ContactSupports multiple flexible bootstrap stagesSupport of third-party signing through certificatesSupport for hardware acceleration, key […]
Rambus Announces Portfolio of Advanced Memory and SerDes PHYs on TSMC N7 Process
https://www.rambus.com/rambus-announces-portfolio-of-advanced-memory-and-serdes-phys-on-tsmc-n7-process/Highlights: GDDR6, HBM2, and 112G Long Reach (LR) interfaces designed for TSMC’s industry-leading N7 process technology expand Rambus’ leading-edge memory and SerDes PHY offerings Portfolio enables critical building blocks for next-generation data center, networking, wireless 5G, high-performance computing (HPC), advanced driver assistance systems (ADAS), artificial intelligence (AI) and machine learning (ML) applications SUNNYVALE, Calif. and […]
High Speed Public Key Accelerator
https://www.rambus.com/security/protocol-engines/high-speed-public-key-accelerator/Security High Speed Public Key Accelerator The Rambus High Speed Public Key Accelerator PKI-IP-154 (EIP-154 formerly the Inside Secure) is a family of cryptographic IP cores designed for full scalability and an optimal performance over gate count ratio. The PKA-IP-154 can be deployed in any semiconductor design that needs key exchange or key generation at […]
HBM2 or GDDR6?
https://www.rambus.com/blogs/hbm2-or-gddr6/Earlier this month, Semiconductor Engineering editor-in-chief Ed Sperling hosted an industry roundtable to discuss new DRAM options and considerations. Frank Ferro, our senior director of product management, represented Rambus, alongside participants from Cadence, Synopsys and Samsung Electronics. Read first our primer on: HBM2E Implementation & Selection – The Ultimate Guide » As Ferro points out, […]
