The EIP-93 Multi-Protocol Engine is a protocol aware packet engine IP for accelerating IPSec, SSL/TLS, and SRTP up to 300Mbps in SoCs. Designed for fast integration, low gate count and full transforms, the EIP-93 provides a reliable and cost-effective embedded IP solution that is easy to integrate into SoC designs.
Protocol-aware IPsec/TLS packet engine with look-aside interface for IoT.
200 Mbps, lowest gate count in the industry, just 100K gates
(ex AMBA interface).
Supported by Driver Development Kit, QuickSec IPsec toolkit,
Secure Boot Toolkit.
The EIP-93 Multi-Protocol Engine is a protocol aware packet engine IP with a look-aside bus interface and a packet transform engine. The Multi-Protocol engine is used as a bus master in the data plane of the system and processes packets with very little CPU intervention. This engine supports an AMBA (AXI, AHB, TCM) or a PLB SoC bus interface and can be delivered in different configurations to support IPsec as well as SSL/TLS. It is the world’s only 100k gate IPsec accelerator (excluding interface).
The EIP-93 is designed to off-load the host processor to improve the speed of protocol operations and reduce power in cost-sensitive networking products, such as: high-end IoT devices; IoT gateways; femtocells; DSL routers; SOHO routers; cable modems; VPN appliances; and surveillance cameras.
Performance for large packet sizes is > 550 Mbps for any supported protocol. IPsec performance for small packet sizes is > 300 Mbps. System clock speed is 250 MHz.
IPsec (IPv4 and IPv6):
SSL3.0 / TLS1.0 / TSL1.1 / TLS1.2 / DTLS:
SRTP packet transforms according to RFC3711:
The cryptographic engine supports the following cryptographic algorithms:
The hash engine supports the following algorithms:
The pseudo random number generator supports:
The DMA controller supports:
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