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Rambus Develops R+™ DDR4/3 PHY on Samsung 28nm LPP Process

Design achieves both high-performance and high-efficiency for networking, computing, and consumer applications

SUNNYVALE, Calif. – February 10, 2015 – Rambus Inc. (NASDAQ:RMBS) today announced it has developed an R+™ DDR4/3 PHY on the Samsung 28nm LPP process. Through the collaboration with Samsung, Rambus has achieved a robust, production-ready R+ DDR4/3 PHY on the power-performance optimized 28nm Low Power Plus (LPP) process. The Rambus design has been characterized at a system level, and can be easily integrated into a SoC.

“With the ongoing demand for data alongside the cloud driving more and more networking, the need for faster speeds and better bandwidth has never been more prevalent,” said Kevin Donnelly, general manager of the Memory and Interface division at Rambus. “Successfully taping out a production-ready R+ DDR4/3 PHY on the Samsung 28nm LPP process is a major step in our strategic and valued partnership. Together we are breaking the necessary ground to achieve the best possible speeds and bandwidth required by today’s consumer and networking devices.”

The Rambus R+ DDR4 multi-modal memory PHY enables customers to differentiate their offerings by providing industry-leading performance while maintaining full compatibility with industry standard DDR4, and DDR3 interfaces. Designed for server, compute, networking and consumer applications, the R+ DDR4 PHY delivers versatile configuration options for both area/power optimized consumer applications and performance intensive compute applications. The DDR4 IP product supports data rates from 800 to 3200Mbps in a low-power process and is available in both PoP and discrete packages “Our high-volume 28nm LPP technology gives SoC designers a robust manufacturing option for a new generation of feature-rich consumer devices.” said Shawn Han, Vice President of Foundry Marketing, Samsung. “We are pleased to be collaborating with Rambus to demonstrate the capabilities of Samsung’s 28nm processes and the design enablement ecosystem available for Samsung’s foundry customer and IP partners.”

The R+ DDR4/3 design leverages the wide range of design enablement support and expertise that Samsung offers, including process design kits (PDKs), DFM kits, analog mixed signal reference flow, extensive implementation services, and silicon proven logic libraries. Rambus also utilized Samsung’s foundry assembly support resources to provide a flip-chip packaging option on the high speed PHY design. In addition, Samsung’s 28nm Low-Power (LP) Gate First High-k Metal Gate (HKMG) process offers considerable power and performance advantages to a growing spectrum of mobile, consumer and IT infrastructure-computing applications.

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About Rambus Inc.
Rambus brings invention to market. Our customizable IP cores, architecture licenses, tools, services, and training improve the competitive advantage of our customer’s products while accelerating their time-to-market. Rambus products and innovations capture, secure and move data. For more information, visit rambus.com.

Rambus and Mobiveil Partner to Bring Pre-Validated Solution to Chip Makers, Delivering Memory Flexibility and Accelerated Time-to-Market

Certified interoperability of DDR4/3, LPDDR3/2 Multi-modal PHY and Universal controller combines industry-leading signal integrity and broad configurability

SUNNYVALE and MILPITAS, Calif. – November 18, 2014 – Rambus Inc. (NASDAQ:RMBS) and Mobiveil today announced they have validated interoperability of the Rambus R+™ DDR4 Multi-modal PHY with the Mobiveil Universal Multiport Memory Controller (UMMC) Core for JEDEC standard DDR4/3 and LPDDR3/2 operation. As part of the overall Rambus IP Cores program, the integrated IP provides chipmakers with a pre-validated, industry standard solution that reduces costs and risk by reducing IP qualification time. In addition, the differentiated memory subsystem brings together the superior signal integrity and low power offered by the Rambus R+ multi-modal PHY with the flexibility of the Mobiveil UMMC in a single, easily integrated solution.

“Partnering with Mobiveil to bring a complete offering to market demonstrates both companies’ commitment to meeting customer needs in the face of increasingly complex and costly SoC development,” said Kevin Donnelly, general manager of the Memory and Interface division at Rambus. “By working in a collaborative manner with companies like Mobiveil, we are addressing chip makers needs with proven and ready-to-use IP blocks that minimize qualification and integration time.”

“Our UMMC Controller Core has successfully proven to be both flexible and configurable for real-time consumer applications,” said Ravi Thummarukudy, chief executive officer of Mobiveil. “Pairing our technology with the Rambus R+ multi-modal PHY provides customers with the best DRAM solution for their particular application without changing the SoC, which substantially minimizes design time and development cycles across a broad number of applications.”

The Rambus R+ DDR4/3, LPDDR3/2 multi-modal PHY delivers industry-leading performance while providing SoC makers a comprehensive array of memory choices, ranging from high-performance to low-power applications. To complement its broad applicability, the R+ DDR4/3 multi-modal PHY delivers versatile configuration options for both area- and power-optimized consumer applications and performance-intensive compute applications. Additionally, the enhanced standards IP cores are designed with system-aware methodology to ensure superior signal integrity and system margin for optimal DRAM vendor interoperability. The PHY is available in several low-power foundry processes and can be configured for both flip-chip and wire bond packages with data rates ranging from 800 to 3200Mbps.

Mobiveil’s UMMC Controller is a highly flexible and configurable design. It is targeted for high bandwidth access and low power consumption such as next-generation mobile, networking and consumer applications. The controller architecture is carefully tailored to achieve reliable high-frequency operation with dynamic power management and rapid system debug capabilities. Its flexible AXI System interface makes it easy to be integrated into a wide range of applications.

Mobiveil has joined the Rambus Partner Program, which will enable further collaboration on other combined IP blocks offerings between the two companies. For additional information on the Rambus Partner Program, visit rambus.com/partners.

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About Rambus Inc.

Rambus brings invention to market. Our customizable IP cores, architecture licenses, tools, services, and training improve the competitive advantage of our customer’s products while accelerating their time-to-market. Rambus products and innovations capture, secure and move data. For more information, visit rambus.com.

About Mobiveil, Inc.

Mobiveil is a fast‐growing technology company that specializes in development of Silicon Intellectual Properties, platforms and solutions for the storage, networking and enterprise markets. Mobiveil team leverages decades of experience in delivering high‐quality, production‐proven, highspeed serial interconnect Silicon IP cores and custom and standard form factor hardware boards to leading customers worldwide.. Mobiveil is headquartered in the Silicon Valley with engineering development centers located in Milpitas, CA, Chennai and Bangalore, India, and sales offices and representatives located in US, Europe, Israel, Japan, Taiwan and People Republic of China. For more information, please visit www.mobiveil.com

Rambus and Northwest Logic Certify Interoperability of DDR4/3 PHY and Controller

Integrated IP block achieves both high-performance and efficiency; tested and validated system-level design provides superior signal integrity and reliability

SUNNYVALE, Calif. and BEAVERTON, Ore. – August 26, 2014 – Rambus Inc. (NASDAQ:RMBS) and Northwest Logic today announced they have validated interoperability of the Rambus R+™ DDR4/3 PHY with the Northwest Logic DDR4/3 SDRAM Controller Core. The combined solution provides customers with a differentiated memory subsystem that brings together the superior signal integrity offered by the Rambus R+ PHY along with the robust Northwest Logic controller core for a proven and easy-to-integrate solution.

“Given the industry’s ongoing demand for higher memory performance to manage greater amounts of data, this integrated solution provides customers with an easy way to integrate a tested and validated PHY/controller combination, ideal for networking, computing, and consumer applications requiring the best possible performance,” said Kevin Donnelly, general manager of the Memory and Interface division at Rambus. “We look forward to continuing our partnership with Northwest Logic and ongoing collaboration between our companies.”

“Our DDR4/3 SDRAM Controller Core has been successfully deployed in a wide variety of customer systems demonstrating high reliability and performance,” said Brian Daellenbach, president of Northwest Logic. “We are excited to offer a complete DDR4/3 solution with Rambus ensuring our customers achieve the best possible combined memory solution for their high data demands.”

The Rambus R+ DDR4/3 PHY enables customers to differentiate their offerings by providing industry-leading performance while maintaining full compatibility with industry-standard DDR4 and DDR3 interfaces. The R+ DDR4/3 PHY delivers versatile configuration options for both area- and power-optimized consumer applications and performance-intensive compute applications. The PHY is available in several low-power foundry processes and can be configured for both flip-chip and wire bond packages with data rates ranging from 800 to 3200Mbps.

The Northwest Logic DDR4/3 SDRAM Controller Cores are part of a family of silicon-proven, high-performance, easy-to-use memory controller cores that provide support for DDR4/3/2/1 LPDDR4/3/2/1, HBM, MRAM, RLDRAM 3/II. In addition, the Northwest Logic DDR4/3 SDRAM Controller Core provides high bus efficiency using request reordering, bank management and look-ahead processing. Northwest Logic also provides AXI/AHB bus interface, Error Correction Code (ECC), Read-Modify-Write and Multi-Port Front-End add-on cores to further simplify user designs. These cores support the highest memory clock rates, require minimal gate count and, as part of the solution, Northwest Logic offers a complete Memory Test Package for validation.

Northwest Logic has joined the Rambus Partner Program, which will enable further collaboration on other combined IP blocks offerings between the two companies. For additional information on the Rambus Partner Program, visit rambus.com/partners.

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Company website: rambus.com
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About Rambus Inc.

Rambus brings invention to market. Our customizable IP cores, architecture licenses, tools, services, and training improve the competitive advantage of our customer’s products while accelerating their time-to-market. Rambus products and innovations capture, secure and move data. For more information, visit rambus.com.

About Northwest Logic

Northwest Logic, founded in 1995 and located in Beaverton, Oregon, provides high-performance, silicon-proven, easy-to-use IP cores including high-performance PCI Express solution (PCI Express 3.0, 2.1 and 1.1 cores and drivers), Memory Interface Solution (DDR4/3/2, LPDDR4/3/2 SDRAM; HBM, MRAM, RLDRAM 3/II), and MIPI Solution (CSI-2, DSI). These solutions support a full range of platforms including ASICs, Structured ASICs and FPGAs. For additional information, visit www.nwlogic.com.

Rambus Enhances LabStation™ Validation Platform

Optimized for ease-of-use and productivity to address the latest challenges of complex IP bring-up and validation

SUNNYVALE, CA — January 28, 2014 — Rambus Inc. (NASDAQ:RMBS) today announced it has enhanced its LabStation™ validation platform to address the latest challenges of complex IP design and integration. The comprehensive test environment provides customers with a tool suite to validate advanced low-power, high-performance memory systems including LPDDR4/3, R+™ LPDDR3, DDR4/3, and R+ DDR4. LabStation™ is available as part of Rambus’ memory and serial link IP core solutions to help customers enhance quality and reduce time-to-market of their chips and systems. The platform is scalable, offers improved accuracy and is proven in complex, high-volume applications.

“The LabStation™ platform addresses the latest low-power, high-performance memory validation challenges, providing our customers with a straightforward and accurate method for testing chips and systems,” said Kevin Donnelly, senior vice president and general manager of the Memory and Interface Division at Rambus. “As we look to drive deeper engagements with our customers, we continue to invest in tools that simplify the design process and enhance the functionality of our IP core solutions.”

Key Features and Benefits of LabStation™

    • Helps customers during bring-up, de-bug and characterization, reducing time-to-market for chips and systems
    • Measures voltage and timing margin eye at target bit error rate (BER), addressing the latest characterization requirements for advanced memory systems
    • Enables automated measurement with on-chip infrastructure to provide testing process simplification and higher accuracy results for high-throughput and small form factor systems, including 2.5 and 3D packaging
    • Provides optimized user interface to improving usability and control of IP for on-chip resources, on-board devices, measurement equipment and 3rd party tools

The Rambus LabStation™ validation platform is currently available for Rambus customers. For additional information visitrambus.com/labstation..

About Rambus Memory and Interfaces Division (MID)

The Rambus Memory and Interfaces Division moves data. MID develops products and services that solve the power, performance, and capacity challenges of the mobile, cloud computing and connected device markets. Rambus enhanced standards-compatible and custom memory and serial link solutions include architectures, memory and chip-to-chip interfaces, DRAM, IP validation tools, and system and IC design services. Developed through our system-aware design methodology, Rambus’ products deliver improved time-to-market and first-time-right quality.

About Rambus

Rambus brings invention to market. Our customizable IP cores, architecture licenses, tools, services, and training improve the competitive advantage of our customer’s products while accelerating their time-to-market. Rambus products and innovations capture, secure and move data. For more information, visit rambus.com.

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