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Rambus Develops R+™ DDR4/3 PHY on Samsung 28nm LPP Process

Design achieves both high-performance and high-efficiency for networking, computing, and consumer applications

SUNNYVALE, Calif. – February 10, 2015 – Rambus Inc. (NASDAQ:RMBS) today announced it has developed an R+™ DDR4/3 PHY on the Samsung 28nm LPP process. Through the collaboration with Samsung, Rambus has achieved a robust, production-ready R+ DDR4/3 PHY on the power-performance optimized 28nm Low Power Plus (LPP) process. The Rambus design has been characterized at a system level, and can be easily integrated into a SoC.

“With the ongoing demand for data alongside the cloud driving more and more networking, the need for faster speeds and better bandwidth has never been more prevalent,” said Kevin Donnelly, general manager of the Memory and Interface division at Rambus. “Successfully taping out a production-ready R+ DDR4/3 PHY on the Samsung 28nm LPP process is a major step in our strategic and valued partnership. Together we are breaking the necessary ground to achieve the best possible speeds and bandwidth required by today’s consumer and networking devices.”

The Rambus R+ DDR4 multi-modal memory PHY enables customers to differentiate their offerings by providing industry-leading performance while maintaining full compatibility with industry standard DDR4, and DDR3 interfaces. Designed for server, compute, networking and consumer applications, the R+ DDR4 PHY delivers versatile configuration options for both area/power optimized consumer applications and performance intensive compute applications. The DDR4 IP product supports data rates from 800 to 3200Mbps in a low-power process and is available in both PoP and discrete packages “Our high-volume 28nm LPP technology gives SoC designers a robust manufacturing option for a new generation of feature-rich consumer devices.” said Shawn Han, Vice President of Foundry Marketing, Samsung. “We are pleased to be collaborating with Rambus to demonstrate the capabilities of Samsung’s 28nm processes and the design enablement ecosystem available for Samsung’s foundry customer and IP partners.”

The R+ DDR4/3 design leverages the wide range of design enablement support and expertise that Samsung offers, including process design kits (PDKs), DFM kits, analog mixed signal reference flow, extensive implementation services, and silicon proven logic libraries. Rambus also utilized Samsung’s foundry assembly support resources to provide a flip-chip packaging option on the high speed PHY design. In addition, Samsung’s 28nm Low-Power (LP) Gate First High-k Metal Gate (HKMG) process offers considerable power and performance advantages to a growing spectrum of mobile, consumer and IT infrastructure-computing applications.

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About Rambus Inc.
Rambus brings invention to market. Our customizable IP cores, architecture licenses, tools, services, and training improve the competitive advantage of our customer’s products while accelerating their time-to-market. Rambus products and innovations capture, secure and move data. For more information, visit rambus.com.

Rambus and Mobiveil Partner to Bring Pre-Validated Solution to Chip Makers, Delivering Memory Flexibility and Accelerated Time-to-Market

Certified interoperability of DDR4/3, LPDDR3/2 Multi-modal PHY and Universal controller combines industry-leading signal integrity and broad configurability

SUNNYVALE and MILPITAS, Calif. – November 18, 2014 – Rambus Inc. (NASDAQ:RMBS) and Mobiveil today announced they have validated interoperability of the Rambus R+™ DDR4 Multi-modal PHY with the Mobiveil Universal Multiport Memory Controller (UMMC) Core for JEDEC standard DDR4/3 and LPDDR3/2 operation. As part of the overall Rambus IP Cores program, the integrated IP provides chipmakers with a pre-validated, industry standard solution that reduces costs and risk by reducing IP qualification time. In addition, the differentiated memory subsystem brings together the superior signal integrity and low power offered by the Rambus R+ multi-modal PHY with the flexibility of the Mobiveil UMMC in a single, easily integrated solution.

“Partnering with Mobiveil to bring a complete offering to market demonstrates both companies’ commitment to meeting customer needs in the face of increasingly complex and costly SoC development,” said Kevin Donnelly, general manager of the Memory and Interface division at Rambus. “By working in a collaborative manner with companies like Mobiveil, we are addressing chip makers needs with proven and ready-to-use IP blocks that minimize qualification and integration time.”

“Our UMMC Controller Core has successfully proven to be both flexible and configurable for real-time consumer applications,” said Ravi Thummarukudy, chief executive officer of Mobiveil. “Pairing our technology with the Rambus R+ multi-modal PHY provides customers with the best DRAM solution for their particular application without changing the SoC, which substantially minimizes design time and development cycles across a broad number of applications.”

The Rambus R+ DDR4/3, LPDDR3/2 multi-modal PHY delivers industry-leading performance while providing SoC makers a comprehensive array of memory choices, ranging from high-performance to low-power applications. To complement its broad applicability, the R+ DDR4/3 multi-modal PHY delivers versatile configuration options for both area- and power-optimized consumer applications and performance-intensive compute applications. Additionally, the enhanced standards IP cores are designed with system-aware methodology to ensure superior signal integrity and system margin for optimal DRAM vendor interoperability. The PHY is available in several low-power foundry processes and can be configured for both flip-chip and wire bond packages with data rates ranging from 800 to 3200Mbps.

Mobiveil’s UMMC Controller is a highly flexible and configurable design. It is targeted for high bandwidth access and low power consumption such as next-generation mobile, networking and consumer applications. The controller architecture is carefully tailored to achieve reliable high-frequency operation with dynamic power management and rapid system debug capabilities. Its flexible AXI System interface makes it easy to be integrated into a wide range of applications.

Mobiveil has joined the Rambus Partner Program, which will enable further collaboration on other combined IP blocks offerings between the two companies. For additional information on the Rambus Partner Program, visit rambus.com/partners.

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About Rambus Inc.

Rambus brings invention to market. Our customizable IP cores, architecture licenses, tools, services, and training improve the competitive advantage of our customer’s products while accelerating their time-to-market. Rambus products and innovations capture, secure and move data. For more information, visit rambus.com.

About Mobiveil, Inc.

Mobiveil is a fast‐growing technology company that specializes in development of Silicon Intellectual Properties, platforms and solutions for the storage, networking and enterprise markets. Mobiveil team leverages decades of experience in delivering high‐quality, production‐proven, highspeed serial interconnect Silicon IP cores and custom and standard form factor hardware boards to leading customers worldwide.. Mobiveil is headquartered in the Silicon Valley with engineering development centers located in Milpitas, CA, Chennai and Bangalore, India, and sales offices and representatives located in US, Europe, Israel, Japan, Taiwan and People Republic of China. For more information, please visit www.mobiveil.com

Rambus and Northwest Logic Certify Interoperability of DDR4/3 PHY and Controller

Integrated IP block achieves both high-performance and efficiency; tested and validated system-level design provides superior signal integrity and reliability

SUNNYVALE, Calif. and BEAVERTON, Ore. – August 26, 2014 – Rambus Inc. (NASDAQ:RMBS) and Northwest Logic today announced they have validated interoperability of the Rambus R+™ DDR4/3 PHY with the Northwest Logic DDR4/3 SDRAM Controller Core. The combined solution provides customers with a differentiated memory subsystem that brings together the superior signal integrity offered by the Rambus R+ PHY along with the robust Northwest Logic controller core for a proven and easy-to-integrate solution.

“Given the industry’s ongoing demand for higher memory performance to manage greater amounts of data, this integrated solution provides customers with an easy way to integrate a tested and validated PHY/controller combination, ideal for networking, computing, and consumer applications requiring the best possible performance,” said Kevin Donnelly, general manager of the Memory and Interface division at Rambus. “We look forward to continuing our partnership with Northwest Logic and ongoing collaboration between our companies.”

“Our DDR4/3 SDRAM Controller Core has been successfully deployed in a wide variety of customer systems demonstrating high reliability and performance,” said Brian Daellenbach, president of Northwest Logic. “We are excited to offer a complete DDR4/3 solution with Rambus ensuring our customers achieve the best possible combined memory solution for their high data demands.”

The Rambus R+ DDR4/3 PHY enables customers to differentiate their offerings by providing industry-leading performance while maintaining full compatibility with industry-standard DDR4 and DDR3 interfaces. The R+ DDR4/3 PHY delivers versatile configuration options for both area- and power-optimized consumer applications and performance-intensive compute applications. The PHY is available in several low-power foundry processes and can be configured for both flip-chip and wire bond packages with data rates ranging from 800 to 3200Mbps.

The Northwest Logic DDR4/3 SDRAM Controller Cores are part of a family of silicon-proven, high-performance, easy-to-use memory controller cores that provide support for DDR4/3/2/1 LPDDR4/3/2/1, HBM, MRAM, RLDRAM 3/II. In addition, the Northwest Logic DDR4/3 SDRAM Controller Core provides high bus efficiency using request reordering, bank management and look-ahead processing. Northwest Logic also provides AXI/AHB bus interface, Error Correction Code (ECC), Read-Modify-Write and Multi-Port Front-End add-on cores to further simplify user designs. These cores support the highest memory clock rates, require minimal gate count and, as part of the solution, Northwest Logic offers a complete Memory Test Package for validation.

Northwest Logic has joined the Rambus Partner Program, which will enable further collaboration on other combined IP blocks offerings between the two companies. For additional information on the Rambus Partner Program, visit rambus.com/partners.

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Company website: rambus.com
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Twitter: @rambusinc
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About Rambus Inc.

Rambus brings invention to market. Our customizable IP cores, architecture licenses, tools, services, and training improve the competitive advantage of our customer’s products while accelerating their time-to-market. Rambus products and innovations capture, secure and move data. For more information, visit rambus.com.

About Northwest Logic

Northwest Logic, founded in 1995 and located in Beaverton, Oregon, provides high-performance, silicon-proven, easy-to-use IP cores including high-performance PCI Express solution (PCI Express 3.0, 2.1 and 1.1 cores and drivers), Memory Interface Solution (DDR4/3/2, LPDDR4/3/2 SDRAM; HBM, MRAM, RLDRAM 3/II), and MIPI Solution (CSI-2, DSI). These solutions support a full range of platforms including ASICs, Structured ASICs and FPGAs. For additional information, visit www.nwlogic.com.

Rambus Introduces High-Performance DDR3 Memory Controller Interface Solution for Consumer Electronics

Demonstrates operation at 1866MT/s in low-cost wire bond package

LOS ALTOS, CALIFORNIA, UNITED STATES – 07/28/2010 – Rambus Inc. (Nasdaq:RMBS), one of the world’s premier technology licensing companies, today announced a high-performance, low-cost DDR3 memory controller interface solution tailored for consumer electronics. Rambus’ DDR3 solution is the first to demonstrate operation in working silicon at a data rate of 1866 megatransfers per second (MT/s) in a low-cost wire bond package. Rambus will demonstrate this technology during the Denali MemCon 2010 conference, at the Hyatt Regency Santa Clara, in Santa Clara, CA. https://www.denali.com/en/memcon/2010

Rambus offers its DDR3 memory controller interface solution to its licensees as a PHY development package (PDP) which allows memory interface designers to customize their DDR3 implementation for their specific application. Rambus’ DDR3 interface solution PDP includes all the necessary building blocks, PHY architecture, schematics, models, generic layout, floor plan, verification IP, implementation documentation, testing documentation, design scripts and simulation files, to ensure design success.

“Our licensees benefit from Rambus’ patented innovations and leading design expertise in a silicon-proven DDR3 interface solution they can customize to their needs,” said Sharon Holt, senior vice president of Licensing and Marketing at Rambus. “This high-performance DDR3 solution tailored for wire bond packaging is ideally suited for a broad range of consumer electronics including next-generation HDTVs, digital set-top boxes and Blu-ray players and recorders.”

The DDR3 interface solution builds on Rambus innovations such as:

  • FlexPhase™ circuits for optimum memory system timing
  • Output driver calibration which supports high data rates and improved system voltage margin
  • On-die termination calibration for improved signaling environment
  • LabStation™ software for rapid bring-up, characterization and validation

Rambus also offers its licensees engineering services such as package design, system board layout, statistically based signal and power integrity analysis, reference guidelines, and bring-up assistance. These services improve time-to-market, support robust operation and high yield in mass production. With over two decades of experience in high-speed design, Rambus is the leader in providing total system solutions for performance memory systems.

About Rambus Inc.

Rambus is one of the world’s premier technology licensing companies. Founded in 1990, the Company specializes in the invention and design of architectures focused on enhancing the end-user experience of electronic systems. Rambus’ patented innovations and breakthrough technologies help industry-leading companies bring superior products to market. Rambus licenses both its world-class patent portfolio, as well as its family of leadership and industry-standard solutions. Headquartered in Los Altos, California, Rambus has regional offices in North Carolina, Ohio, India, Germany, Japan, and Taiwan. Additional information is available at www.rambus.com.

Rambus And Cadence Collaborate And Deliver Fully Integrated And Independently Verified PCI Express Solutions

New offering combines best-of-breed design and verification IP for high-quality, low-risk, and simplified design integration

LOS ALTOS, CALIFORNIA, UNITED STATES – 09/04/2007 – Rambus Inc. (NASDAQ:RMBS), one of the world’s premier technology licensing companies specializing in high-speed memory architectures, and Cadence® Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic-design innovation, today announced fully integrated and independently verified PCI Express® solutions. The two companies have collaborated and now offer highly adaptable PCI Express digital cores and PHY IP from Rambus, tightly integrated and verified with Cadence verification IP.

The result of the joint work provides SOC designers with an independently verified solution that seamlessly integrates Rambus’ design IP with the automated verification IP from Cadence. This solution helps shorten time to market with an efficient, predictable, and low-risk SOC design and verification to enhance the quality of the end product. In addition, the solution includes the Cadence Compliance Management System (CMS) featuring a PCI Express compliance verification plan (vPlan) and compliance tests, both of which have been specifically customized to the Rambus design IP. The CMS provides an automated plan and metric-driven solution to reach high levels of coverage without the need to develop tests. Based on the Cadence Incisive® Plan-to-Closure methodology, the offering allows customers to maximize design quality while minimizing protocol expertise and verification time.

“As a company developing cutting-edge technology, it is critical that we build our solutions on proven, tightly integrated technology,” said John F. Brown, vice president, Engineering at Tilera Corporation. “Using the combination of the Rambus configurable PCI Express Digital Controller with the independently developed verification IP from Cadence enables the rapid and successful IP integration we are looking for.”

“Through this collaboration, we are able to provide an ideal combination of Cadence verification IP and methodology expertise with Rambus design IP. This solution leverages the strengths of both companies, speeding up the IP integration process and increasing productivity and quality for customers,” said Steve Glaser, vice president of Marketing at Cadence’s Verification Division. “Designers will gain a higher degree of predictability with the functional coverage provided by the Rambus design-IP-specific CMS. The result gives our mutual customers confidence that they will get to market on schedule with a quality product.”

The PCI-SIG-compliant and interoperability-tested Rambus PCI Express solution has been implemented and shipped in numerous high-volume applications. Rambus digital core IP has adaptable application interfaces that minimize the amount of glue logic required for integration. Rambus PHY cells are delivered as complete serial communication cells, optimized for maximum production yield.

“Increasingly powerful computing and consumer electronics applications require IP solutions that are flexible and seamlessly integrate into our customers’ designs,” said Tim Messegee, vice president of Marketing at Rambus Inc. “With this collaboration, Cadence and Rambus continue our commitment to provide the market with superior integrated IP and EDA solutions that accelerate time to market and reduce design risk.”

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