With the insatiable need for higher bandwidth in state-of-the-art AI/ML training and HPC, the HBM standard has been on a rapid pace of improvement. The newly standardized HBM3 generation doubles the data rate to 6.4 Gb/s that offers up to 819 GB/s of memory bandwidth between an accelerator and a single HBM3 DRAM device. Memory interface technology expert, Frank Ferro will discuss how the Rambus 8.4 Gb/s HBM3 Memory Subsystem can provide the headroom and scalability needed for implementing state-of-the-art HBM designs.
Controllers
Memory Bandwidth Races Higher with HBM3
Join memory expert Frank Ferro for a live webinar as he discusses what changes come with the new generation of HBM, and how the Rambus HBM3 memory subsystem can help designers unleash the full power of their HBM3-enabled accelerators and SoCs.
CXL and IDE: Important Considerations of Protecting High Speed Interconnects
Hear Rambus and Siemens discuss the background of IDE, the threat models it addresses, and how zero latency IDE’s can provide assurances to CXL adopters. Design and verification engineers and managers won’t want to miss this webinar to understand how to incorporate and validate this essential standard in their designs.
Selection and Implementation of a PCIe 5.0 Subsystem
The latest generation of the PCI Express, PCIe 5.0, advances performance to 32 GT/s in support of advanced applications including 400G Ethernet. In this webinar, Rambus technology experts Malini Narayanamoorthi and Vinitha Seevaratnam discuss the selection and implementation considerations for PCI Express solutions. A demonstration of the silicon-proven Rambus PCIe 5.0 interface solution consisting of integrated PHY and memory controller will be shown.
- In this webinar, you will:
Learn about applications for PCI Express technology
Understand the features and benefits of the Rambus interface
See a demo of the silicon-proven Rambus PCIe 5.0
Selecting the Right High Bandwidth Memory Solution
An exponentially rising tide of data has led to the development of application-specific silicon to tackle the requirements of demanding workloads such as AI/ML training, Advanced Driver Assistance Systems (ADAS) for automotive, network graphics and HPC. To keep these processors and accelerators fed requires state-of-the-art memory solutions that deliver extremely high bandwidth. Frank Ferro will discuss design and implementation considerations of HBM2E and GDDR6 memory subsystems to address the bandwidth needs of next-generation computing applications.
- In this webinar, you will learn:
Applications for HBM2E and GGR6 Memory
Features and benefits of the Rambus interface
Implementation considerations and support
Next-Generation Displays: An Integrated IP Solution from Mixel, Rambus & Hardent
Displays for next-generation smartphones, AR/VR devices, and automotive systems all require more bandwidth than ever before. Using a combination of VESA Display Stream Compression (DSC) with the MIPI Display Serial Interface (DSI-2) technology, designers can achieve display resolutions up to 8K without compromise to video quality, battery life or cost. This presentation will showcase a fully integrated off-the-shelf display IP solution consisting of Mixel (C-PHY/D-PHY Combo), Rambus (DSI-2 Controller), and Hardent (VESA DSC) IP that delivers state-of-the-art performance. Display use cases addressed by the integrated solution will be discussed. Audience Q&A follows the presentation.
