Join Rambus and Cadence and learn how they worked together to develop an integrated memory subsystem that is deployed widely in end-customer systems using TSMC advanced nodes. Also discussed will be the signal integrity challenges of implementing GDDR6 and GDDR7 at these high data rates.
Interface IP
Unleashing the Performance of AI Training with HBM4
AI training models are growing in both size and sophistication at a breathtaking rate, requiring ever greater bandwidth and capacity. With its unique 2.5D/3D architecture, HBM4 can deliver Terabytes per second of bandwidth and unprecedented capacity in an extremely compact form factor. Join Kevin Yee from Samsung and Nidish Kamath from Rambus discuss the design considerations of HBM4 memory subsystems (PHY, Memory Controller, and Packaging) in next-generation AI SoCs.
Verifying the next generation High Bandwidth Memory controllers for AI and HPC applications
High Bandwidth Memory (HBM) has revolutionized AI, machine learning, and High-Performance Computing by significantly increasing data transfer speeds and alleviating performance bottlenecks. The introduction of next-generation HBM4 is especially transformative, enabling faster training and execution of complex AI models. JEDEC has announced that the HBM4 specification is nearing finalization. In this webinar, you will learn how Siemens’s scalable and customizable Avery HBM Verification IP helps companies like Rambus verify their industry-leading HBM4 Controller IP through rigorous testing to ensure reliability and performance.
From Training to Inference: HBM, GDDR & LPDDR Memory
Join Nidish Kamath, director of product management for Rambus Memory Controller IP, as he dives into the HBM, GDDR, and LPDDR solutions that address AI training and inference workload requirements in this webinar.
Navigating the Dynamics of IP Licensing for Data Center & AI
Raj Uppala, Senior Director of Marketing and Partnerships at Rambus, explores the complexities of IP licensing for emerging data center and AI applications.
Why PCIe and CXL are Critical Interconnects for the AI Era
Join Lou Ternullo, Senior Director of IP Product Management at Rambus, as he discusses the critical role of PCIe and CXL interconnects in enabling the AI-driven data centers of tomorrow in this on-demand webinar.
