Join memory interface technology expert Frank Ferro as he discusses the capabilities of, and design considerations for, the upcoming 3rd- generation of high-bandwidth memory: HBM3.
Webinars
CXL and IDE: Important Considerations of Protecting High Speed Interconnects
Hear Rambus and Siemens discuss the background of IDE, the threat models it addresses, and how zero latency IDE’s can provide assurances to CXL adopters. Design and verification engineers and managers won’t want to miss this webinar to understand how to incorporate and validate this essential standard in their designs.
More capacity and more bandwidth: DDR5 memory enables next-generation data centers
Hear Shane Rau, Research Vice President at IDC discuss the market and technology trends surrounding the DDR5 transition, including workloads, hardware needs, market perspectives and industry timing. Joining him, John Eble, Vice President of Product Marketing at Rambus will examine the changes from DDR4 to DDR5 that are enabling more memory capacity and bandwidth critical to scaling future data centers.
