[April 14 @ 11am PT] Join Neeraj Paliwal, general manager of the Rambus Security IP business, and John McHale, EVP & Group Editorial Director of Military Embedded Systems, as they discuss how hardware level protection is the key to building the foundation of security for data and electronic systems.
Webinars
Memory Bandwidth Races Higher with HBM3
Join memory expert Frank Ferro for a live webinar as he discusses what changes come with the new generation of HBM, and how the Rambus HBM3 memory subsystem can help designers unleash the full power of their HBM3-enabled accelerators and SoCs.
Protecting Government Systems: Addressing Growing CyberSecurity Threats With Hardware-Level Security
[Feb 22 @ 11am PT] In this webinar, Adelaide O’Brien, Research Director, Government Digital Transformation Strategies of IDC and Neeraj Paliwal, general manager of Security IP and Rambus, will discuss the need and solutions for protecting systems at the foundational hardware level.
Stopping Stealthy Counterfeit Chips with PUF Helper-Data Images
PUFs, physically unclonable functions, are mixed-signal circuits which rely on variations unique to a specific chip in order to self-generate a digital “fingerprint.” These fingerprints can be used as the basis of cryptographic keys. While that’s useful, the real power of PUFs is leveraging their unclonable transformation function to enable a challenge-response mechanism that can distinguish an authentic chip from a perfect adversarial clone at any time after the original chip is fielded. In this webinar, Scott Best, Technical Director of Rambus Security IP, will describe the methods that PUF helper-data images generated during the chip manufacturing process can be employed to end the risk of undetectable counterfeit chips.
Bring on the Bandwidth with HBM3 Memory
Join memory interface technology expert Frank Ferro as he discusses the capabilities of, and design considerations for, the upcoming 3rd- generation of high-bandwidth memory: HBM3.
CXL and IDE: Important Considerations of Protecting High Speed Interconnects
Hear Rambus and Siemens discuss the background of IDE, the threat models it addresses, and how zero latency IDE’s can provide assurances to CXL adopters. Design and verification engineers and managers won’t want to miss this webinar to understand how to incorporate and validate this essential standard in their designs.
