Moore’s Law has been the force that has shaped the modern world enabling chips with billions of transistors. Yet today, when we need Moore’s Law more than ever, the rate of semiconductor scaling is slowing, requiring system architects to take a new approach to continue the pace of performance gains in computing. Heterogenous compute architectures with purpose-built silicon hold the key to the next great chapter of semiconductor industry as we enter the accelerator era.
Webinars
Navigating the Intersection of Safety and Security
Vehicle systems and the semiconductors used within them are some of the most complex electronics seen today. Ensuring these systems are both functionally safe and secure from cyberattacks is mission critical. Join us for this webinar where Thierry Kouthon of Rambus, and Ann Keffer of Siemens will discuss hardware solutions for securing automotive electronics and how functional safety tools from Siemens can help ensure these solutions meet the requirements of ISO 26262.
Protecting Devices with Security Anchored in Hardware
[April 14 @ 11am PT] Join Neeraj Paliwal, general manager of the Rambus Security IP business, and John McHale, EVP & Group Editorial Director of Military Embedded Systems, as they discuss how hardware level protection is the key to building the foundation of security for data and electronic systems.
Memory Bandwidth Races Higher with HBM3
Join memory expert Frank Ferro for a live webinar as he discusses what changes come with the new generation of HBM, and how the Rambus HBM3 memory subsystem can help designers unleash the full power of their HBM3-enabled accelerators and SoCs.
Protecting Government Systems: Addressing Growing CyberSecurity Threats With Hardware-Level Security
[Feb 22 @ 11am PT] In this webinar, Adelaide O’Brien, Research Director, Government Digital Transformation Strategies of IDC and Neeraj Paliwal, general manager of Security IP and Rambus, will discuss the need and solutions for protecting systems at the foundational hardware level.
Stopping Stealthy Counterfeit Chips with PUF Helper-Data Images
PUFs, physically unclonable functions, are mixed-signal circuits which rely on variations unique to a specific chip in order to self-generate a digital “fingerprint.” These fingerprints can be used as the basis of cryptographic keys. While that’s useful, the real power of PUFs is leveraging their unclonable transformation function to enable a challenge-response mechanism that can distinguish an authentic chip from a perfect adversarial clone at any time after the original chip is fielded. In this webinar, Scott Best, Technical Director of Rambus Security IP, will describe the methods that PUF helper-data images generated during the chip manufacturing process can be employed to end the risk of undetectable counterfeit chips.
