Security Challenges in a World of AI Everywhere
In this webinar, Scott Best, Senior Director of Anti-Tamper Technology at Rambus, explores the security challenges associated with AI chips and their
At Rambus, we create cutting-edge semiconductor and IP products, providing industry-leading chips and silicon IP to make data faster and safer.
HBM4E Advances Bandwidth Performance for AI Training
Upcoming and On-demand Webinars at Rambus
Check out our library of upcoming and on-demand webinars, and hear from our experts about topics ranging from high speed memory solutions, security IP, IoT and beyond.
The Road Ahead for Main Memory in the Data Center
In this webinar, Carlos Weissenberg, Product Marketing Manager for Memory Interface Chips at Rambus, discusses the increasing demands for memory driven by
The Impact of AI 2.0 on Memory & Interconnect Technology
Steven Woo, Fellow and Distinguished Inventor at Rambus Labs, explores the transformative impact of AI 2.0 on memory and interconnect technology. He
The Ultimate Guide to Secure Silicon: Certified Silicon IP
The Ultimate Guide to Secure Silicon webinar series focuses on cutting-edge design and implementation techniques for hardware security. This series is perfect
The Ultimate Guide to Secure Silicon: Quantum Safe Cryptography
The Ultimate Guide to Secure Silicon webinar series focuses on cutting-edge design and implementation techniques for hardware security. This series is perfect
The Ultimate Guide to Secure Silicon: MACsec & IPsec
The Ultimate Guide to Secure Silicon webinar series focuses on cutting-edge design and implementation techniques for hardware security. This series is perfect
The Ultimate Guide to Secure Silicon: Root of Trust
The Ultimate Guide to Secure Silicon webinar series focuses on cutting-edge design and implementation techniques for hardware security. This series is perfect
AI 2.0 Driving Demand for Memory Performance
[July 24 @ 11am PT] Hear from IDC guest speaker, Jeff Janukowicz, and Rambus’ John Eble, as they set the market context
Unlocking the Potential of CXL 3.1 and PCIe 6.1 for Next-Generation Data Centers
[Live on Feb 28] Increased demand for bandwidth, capacity and compute, coupled with the implications for increased data center costs, are the
Quantum Safe Cryptography: Protecting Devices and Data in the Quantum Era
[Live on January 10, 2024] Quantum computers will eventually become powerful enough to break current asymmetric encryption, placing important data and assets
Memory Systems for AI in the Data Center
Developments in generative AI and Large Language Models are moving at a lightning pace. Incredible amounts of data must be processed and moved to train models which at their largest now exceed one trillion parameters. Join Rambus Fellow and Distinguished Inventor, Dr. Steven Woo, as he discusses the memory and interface technologies critical to powering next-generation computing architectures for AI/ML in the data center and beyond.
LPDDR5X: Delivering High Bandwidth and Power Efficiency
The bandwidth and low power characteristics of LPDDR make it an increasingly attractive choice of memory for applications in IoT, automotive, and edge computing. LPDDR5X takes performance to the next level with a data rate of up to 8.5 Gbps. Join Vinitha Seevaratnam to learn which applications can benefit from using LPDDR memory.
System Level Design Considerations for PCIe 6.0
PCIe 6.0 offers many new and exciting features including a 64 GT/s data rate, PAM4 signaling, forward error correction, and a low power L0p mode. In this presentation, Lou Ternullo will walk you through all the system design considerations you will need to know before getting started on your PCIe 6.0 design, including how to get the most out of each of the PCIe devices.
Leveraging VESA Video Compression & MIPI DSI-2 for High-Performance Displays
Visually lossless video compression is essential for handling the growing bandwidth requirements of cutting-edge displays with higher resolutions, faster refresh rates, and greater pixel depths. This presentation will show designers how they can develop cutting-edge display products without compromising on display quality, battery life or cost using a combination of VESA video compression and MIPI DSI-2 technology.
Meeting the Needs of Generative AI Training with HBM3
Generative AI training models are growing in both size and sophistication at a lightning pace, requiring more and more bandwidth. With its unique 2.5D/3D architecture, HBM3 can deliver Terrabytes per second of bandwidth at a system level. Join Frank Ferro to hear how HBM helps designers address the needs of state-of-the-art AI training models.
