At Rambus, we create cutting-edge semiconductor and IP products, providing industry-leading chips and silicon IP to make data faster and safer.
HBM4E Advances Bandwidth Performance for AI Training
Check out our library of upcoming and on-demand webinars, and hear from our experts about topics ranging from high speed memory solutions, security IP, IoT and beyond.
PCIe 6.0 offers many new and exciting features including a 64 GT/s data rate, PAM4 signaling, forward error correction, and a low power L0p mode. In this presentation, Lou Ternullo will walk you through all the system design considerations you will need to know before getting started on your PCIe 6.0 design, including how to get the most out of each of the PCIe devices.
Visually lossless video compression is essential for handling the growing bandwidth requirements of cutting-edge displays with higher resolutions, faster refresh rates, and greater pixel depths. This presentation will show designers how they can develop cutting-edge display products without compromising on display quality, battery life or cost using a combination of VESA video compression and MIPI DSI-2 technology.
Generative AI training models are growing in both size and sophistication at a lightning pace, requiring more and more bandwidth. With its unique 2.5D/3D architecture, HBM3 can deliver Terrabytes per second of bandwidth at a system level. Join Frank Ferro to hear how HBM helps designers address the needs of state-of-the-art AI training models.
GDDR6 memory offers an impressive combination of bandwidth, capacity, latency and power. Frank Ferro will discuss how these features make it the ideal memory choice for AI/ML inference at the edge and highlight some of the key design considerations you need to keep in mind when implementing GDDR6 memory at ultra-high data rates.
With the industry now firmly on the path to enabling the next generation of servers with DDR5 memory, this presentation will look at what’s next in the DDR5 journey. Hear from John Eble on how DDR5 will scale to advanced performance levels, be deployed in new applications beyond RDIMMs, and how it is tailored for client computing systems.
The swift advancements and growing intricacy of highly interconnected semiconductor systems have led to numerous security challenges that pose risks to the integrity, reliability, and performance of modern AI-driven systems. This presentation delves into the primary emerging security threats, such as supply chain attacks, intellectual property theft, hardware Trojans, side-channel attacks, fault injection attacks, and the looming threat of quantum computers. Neeraj Paliwal will examine the consequences of these threats across different industries and discuss how a hardware “secure by design” architectural approach is essential to secure semiconductor systems.
A Root of Trust is the secure security foundation for a semiconductor or electronic system. In this presentation, Bart Stevens will guide you through the labyrinth of Root of Trust designs, including what problems they can solve and what solutions are available to implement in your next silicon design.
Quantum computers will eventually become powerful enough to break traditional asymmetric cryptographic methods, that is, some of the most common security protocols used to protect sensitive electronic data. This presentation will highlight the recent developments in post-quantum cryptography and discuss how designers can get ready for the quantum era.
A side-channel attack (SCA) is a security exploit that attempts to extract secrets from a chip or a system. This presentation will give an overview of some of the most common types of SCA and highlight the countermeasures that designers can implement to diminish risk in low-power IoT designs.
Automotive systems, and the semiconductors used within them, are some of the most complex electronics seen today. That complexity is set to dramatically rise as cars reach new levels of automation. This presentation will explore how designers can navigate the delicate balance between achieving new levels of performance and automation, while meeting the safety and security requirements unique to the automotive industry.
Data centers continue to adopt full line-rate security at various levels and use cases. Layer 2 (MACsec) and Layer 3 (IPsec) protocols are used to protect either full links or specific subnets or even customer-driven virtual networks. The integration of multiple security protocols is becoming an important requirement for data center silicon that aims to support multiple use cases. Join Maxim Demchenko to learn about the requirements for adding MACsec/IPsec into data center silicon designs.
There is a growing industry consensus on the imperative of incorporating memory encryption in computing architectures for protecting data in use. Designing and implementing a secure memory encryption system can be complex and comes with unique challenges from both the memory and security technology perspectives. Join Ajay Kapoor to learn how memory encryption can be used in your next data center design to enable confidential computing.
The semiconductor industry is the lifeblood of the digital economy. The design, manufacturing and consumption of chips is a global ecosystem, and competition is fierce as scaling and cost reductions based on Moore’s law are diminishing. Counterfeit and other unauthorized chips create real risks in areas of reliability, functionality, performance and safety. This presentation will discuss how semiconductor companies can protect their IP and business by securely provisioning silicon, and the means to provide the ecosystem-wide capabilities needed to verify the identity and provenance of semiconductor devices.
This webinar will explore how GDDR6, operating at data rates up to 24 Gigabits per second (Gb/s) supports the memory and performance
The latest generation of PCI Express® (PCIe®) 6.0, advances performance to 64 GT/s in support of advanced data center workloads and networking.
