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At Rambus, we create cutting-edge semiconductor and IP products, providing industry-leading chips and silicon IP to make data faster and safer.

HBM4E Advances ​Bandwidth Performance for AI Training

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Upcoming and On-demand Webinars at Rambus

Check out our library of upcoming and on-demand webinars, and hear from our experts about topics ranging from high speed memory solutions, security IP, IoT and beyond.

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Accelerating Data Interconnects with PCI Express™ 6.0 & 5.0 Interface IP

Accelerating Data Interconnects with PCI Express™ 6.0 & 5.0 Interface IP

The latest generation of the PCI Express, PCIe™ 6.0, advances performance to 64 GT/s in support of advanced workloads and networking. In this presentation, interface technology expert, Arjun Bangre will discuss the changes implemented in PCI Express 6.0, such as PAM4 signaling and low-latency forward error correction (FEC). In addition, Arjun Bangre will contrast PCIe 6.0 and 5.0 and explain how Rambus can support the PCIe interface your next design requires.

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GDDR6 Memory Enables High-Performance Inferencing

GDDR6 Memory Enables High-Performance Inferencing

A rapid rise in the size and sophistication of inferencing models has necessitated increasingly powerful hardware deployed at the network edge and in the endpoint devices. To keep these inferencing processors and accelerators fed with data requires a state-of-the-art memory solution that delivers extremely high bandwidth. Frank Ferro will discuss the design and implementation considerations of GDDR6 memory subsystems to address the bandwidth needs of these next-generation inferencing engines.

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Implementing CXL™ 2.0 Interconnect Solutions

Implementing CXL™ 2.0 Interconnect Solutions

Compute Express Link™ (CXL) has evolved rapidly since its launch in 2019 and is slated for debut in the next generation of server platforms coming later this year. While it builds on the same physical layer as PCI Express, CXL implements unique features at the controller level to enable memory cache coherency between a host and multiple types of connected devices including smart NICs, accelerators and memory expansion devices.

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Memory Bandwidth for AI/ML Races Higher with HBM3

Memory Bandwidth for AI/ML Races Higher with HBM3

With the insatiable need for higher bandwidth in state-of-the-art AI/ML training and HPC, the HBM standard has been on a rapid pace of improvement. The newly standardized HBM3 generation doubles the data rate to 6.4 Gb/s that offers up to 819 GB/s of memory bandwidth between an accelerator and a single HBM3 DRAM device. Memory interface technology expert, Frank Ferro will discuss how the Rambus 8.4 Gb/s HBM3 Memory Subsystem can provide the headroom and scalability needed for implementing state-of-the-art HBM designs.

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Advancing Computing in the Accelerator Age

Advancing Computing in the Accelerator Age

Moore’s Law has been the force that has shaped the modern world enabling chips with billions of transistors. Yet today, when we need Moore’s Law more than ever, the rate of semiconductor scaling is slowing, requiring system architects to take a new approach to continue the pace of performance gains in computing. Heterogenous compute architectures with purpose-built silicon hold the key to the next great chapter of semiconductor industry as we enter the accelerator era.

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Emerging Compute Architectures for the Evolving Data Center

Emerging Compute Architectures for the Evolving Data Center

As the world has become increasingly connected, processing continues to evolve from the familiar cloud computing paradigm. The vast profusion of IoT devices has contributed to the exponential rise in data volume. Greater intelligence is moving to the edge of the network and to the end points themselves to provide greater, real-time functionality. The implications for global network infrastructure are profound and there are significant developments in computing architectures which will shape the future data center.

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Data Center Dynamics

Data Center Dynamics

Ed Sperling, Editor in Chief of Semiconductor Engineering moderates a far-ranging roundtable on the dynamics shaping the future of the data center. Rambus Fellow and Distinguished Inventor, Steven Woo, discusses the macro trends and their impact on compute and network device architectures. Technology leaders from across Rambus will share the chip and IP solutions that can take data center performance and security to the next level.

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