At Rambus, we create cutting-edge semiconductor and IP products, providing industry-leading chips and silicon IP to make data faster and safer.
HBM4E Advances Bandwidth Performance for AI Training
Check out our library of upcoming and on-demand webinars, and hear from our experts about topics ranging from high speed memory solutions, security IP, IoT and beyond.
Compute Express Link™ (CXL) has evolved rapidly since its launch in 2019 and is slated for debut in the next generation of server platforms coming later this year. While it builds on the same physical layer as PCI Express, CXL implements unique features at the controller level to enable memory cache coherency between a host and multiple types of connected devices including smart NICs, accelerators and memory expansion devices.
With the insatiable need for higher bandwidth in state-of-the-art AI/ML training and HPC, the HBM standard has been on a rapid pace of improvement. The newly standardized HBM3 generation doubles the data rate to 6.4 Gb/s that offers up to 819 GB/s of memory bandwidth between an accelerator and a single HBM3 DRAM device. Memory interface technology expert, Frank Ferro will discuss how the Rambus 8.4 Gb/s HBM3 Memory Subsystem can provide the headroom and scalability needed for implementing state-of-the-art HBM designs.
Moore’s Law has been the force that has shaped the modern world enabling chips with billions of transistors. Yet today, when we need Moore’s Law more than ever, the rate of semiconductor scaling is slowing, requiring system architects to take a new approach to continue the pace of performance gains in computing. Heterogenous compute architectures with purpose-built silicon hold the key to the next great chapter of semiconductor industry as we enter the accelerator era.
Vehicle systems and the semiconductors used within them are some of the most complex electronics seen today. Ensuring these systems are both
[April 14 @ 11am PT] Join Neeraj Paliwal, general manager of the Rambus Security IP business, and John McHale, EVP & Group
Join memory expert Frank Ferro for a live webinar as he discusses what changes come with the new generation of HBM, and
[Feb 22 @ 11am PT] In this webinar, Adelaide O’Brien, Research Director, Government Digital Transformation Strategies of IDC and Neeraj Paliwal, general
PUFs, physically unclonable functions, are mixed-signal circuits which rely on variations unique to a specific chip in order to self-generate a digital
Join memory interface technology expert Frank Ferro as he discusses the capabilities of, and design considerations for, the upcoming 3rd- generation of
Hear Rambus and Siemens discuss the background of IDE, the threat models it addresses, and how zero latency IDE’s can provide assurances
Hear Shane Rau, Research Vice President at IDC discuss the market and technology trends surrounding the DDR5 transition, including workloads, hardware needs,
As the world has become increasingly connected, processing continues to evolve from the familiar cloud computing paradigm. The vast profusion of IoT devices has contributed to the exponential rise in data volume. Greater intelligence is moving to the edge of the network and to the end points themselves to provide greater, real-time functionality. The implications for global network infrastructure are profound and there are significant developments in computing architectures which will shape the future data center.
Ed Sperling, Editor in Chief of Semiconductor Engineering moderates a far-ranging roundtable on the dynamics shaping the future of the data center. Rambus Fellow and Distinguished Inventor, Steven Woo, discusses the macro trends and their impact on compute and network device architectures. Technology leaders from across Rambus will share the chip and IP solutions that can take data center performance and security to the next level.
Providing Layer 2 security, MACsec is becoming the predominant solution for safeguarding network traffic. While network security is increasingly a de facto requirement, there is a growing trend of protecting the SoC interfaces as well, including short distance ones such as PCI Express (PCIe) and those to off-chip memory. In this webinar, Rambus security expert, Gijs Willemse, will discuss the design and implementation of hardware-based MACsec security and trends for high-performance inline encryption.
With the rising value of AI/ML spanning training and inference models and data, as well as the AI hardware itself, the threats from adversaries are greater than ever. As such, a security strategy for AI/ML workloads and hardware needs to offer far more than secure boot and authentication. Rambus security expert, Bart Stevens will discuss how a hardware root of trust can be the foundation for AI/ML security through defense in depth, partitioning of secure operations, and state-of-the-art protections from side channel attacks.
