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Home > Archives

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Northwest Logic’s DMA Back-End Core is NOW shipping as part of Xilinx’s Spartan-6 and Virtex-6 Connectivity Kits

New Xilinx Virtex-6 and Spartan-6 FPGA Connectivity Development Kits Include Northwest Logic DMA Engine IP

High-Performance DMA Engine IP is a Key Component of Xilinx’s Comprehensive Targeted Reference Design for High-Speed Connectivity
SAN JOSE, Calif., December 8, 2009 – Xilinx Inc. (NASDAQ: XLNX) today announced the availability of the new Xilinx® Virtex®-6 and Spartan®-6 FPGA Connectivity Development Kits that provide a comprehensive, easy-to-use, and hardware validated development environment. A key component of the new kits is the Connectivity Targeted Reference Designs that contain Northwest Logic’s high-performance, scatter-gather DMA Engine IP. The Northwest Logic® DMA Engine IP, in combination with the other elements of the kits, provides high-bandwidth operation for a wide variety of PCI Express®-based applications enabling customers to quickly develop and deploy designs for a broad range of high-speed connectivity applications.

The Xilinx Connectivity Kits (www.xilinx.com/products/technology/connectivity.html) minimize overall development time by providing a fully integrated development environment complete with FPGA boards, cables, documentation, design tools, and IP (intellectual property) cores integrated into Targeted Reference Designs. As a key member of the Xilinx Alliance Program (www.xilinx.com/alliance), Northwest Logic collaborated with Xilinx from the initial definition through final release of the connectivity Targeted Reference Designs, to ensure they provide high-bandwidth operation under real system conditions. This performance can be validated by customers using the performance monitor interface built into the Targeted Reference Design.

The Northwest Logic DMA Back-End Core provides a complete, high-performance DMA engine optimized to work with Xilinx integrated PCI Express Endpoint Block plus core and external memory interface soft IP in Virtex-6 FPGAs and hard memory interface IP available in Spartan-6 FPGAs. The Northwest Logic DMA engine includes target and register interfaces and can automatically fetch DMA descriptors or use DMA descriptors provided locally.

“Starting with a pre-validated Target Reference Design will enable our customers to meet the short design cycles time required in today’s competitive environment,” said Xilinx Sr. Director of Platform, Solutions and Services Marketing Tim Erjavec. “Because system verification and testing takes up the largest portion of FPGA design time, we’ve worked closely with Northwest Logic to ensure that users of the Connectivity Development Kits have a highly productive experience right out of the box using a fully integrated reference design.”

The collaboration between Xilinx and Northwest Logic is one example of the broad ecosystem Xilinx is building to bring industry-leading IP components to its customers as part of fully integrated and tested Xilinx Targeted Reference Designs. “By collaborating with Xilinx from the very start of the project we’ve ensured the Virtex-6 and Spartan-6 FPGA Connectivity Development kits will deliver optimal DMA-based performance in a wide variety of PCI Express applications,” said Northwest Logic President Brian Daellenbach. “At the same time we’ve minimized the system development effort required so that our mutual customers can quickly develop and deploy their unique designs.”

The Xilinx Connectivity Targeted Design Platforms provide a starting point for a broad variety off SoC (system-on-chip) applications including:

  • Wired communications routers and switchers
  • Wireless radio head and Baseband processing
  • Audio Video Broadcast control switchers and routers
  • Automotive driver assistance control applications
  • Automotive infotainment applications
  • Consumer set top boxes

The Xilinx Spartan-6 FPGA Connectivity Kit is complete and easy-to-use, enabling designs with industry-standard high-speed serial protocols including PCI Express (version 1.1), Ethernet (GMII, SFP), and DDR3 SDRAM (using built-in hard memory controller) as well as enabling designs using other serial standards and proprietary implementations up to 3.125Gbps and multiple parallel protocols including 3.3V I/O standards.

Similarly, the Xilinx Virtex-6 FPGA Connectivity Development Kit enables advanced connectivity designs with PCI Express 1.1/2.0, Ethernet (GMII, SFP, XAUI), SATA, and other proprietary high-speed serial protocols with line rates up to 6.5Gbps, as well as multiple parallel standards running at ~ 1.4Gbps with SelectIO™ technology.

The Spartan-6 FPGA Connectivity kit is available for order today including a full version the Northwest Logic DMA Back-End Core for $2,495. The Virtex-6 FPGA Connectivity kit will be available in January and includes an evaluation version of the Northwest Logic DMA Back-End Core for $2,995.

For information on Northwest Logic and available IP and solutions please visit www.nwlogic.com/products/pci-express-solution/. For more information on Xilinx Connectivity Targeted Design Platforms please visit www.xilinx.com/products/technology/connectivity.html.

About Xilinx

Xilinx is the worldwide leader in complete programmable logic solutions. For more information, visit www.xilinx.com.

About Northwest Logic

Northwest Logic, founded in 1995 and located in Beaverton, Oregon, provides high performance, easy-to-use IP cores for ASICs and FPGAs. These IP cores include memory controller, PCIe, PCI-X, PCI and MIPI cores. For additional information, visit www.nwlogic.com.

Editorial Contact:
Bruce Fienberg
Xilinx, Inc.
408-879-4631
bruce.fienberg@xilinx.com

XILINX, the Xilinx Logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI Express and PCIe are trademarks of PCI-SIG. All other trademarks are the property of their respective owners.

Northwest Logic Chooses ChipStart as North America and EMEA Distribution Partner

Agreement includes distribution of Expresso Solution for PCI Express ®, Memory Interface and MIPI Solutions

Beaverton, Oregon and Palo Alto, California, May 11, 2009 – Northwest Logic, a leading semiconductor intellectual property provider, announced it has selected ChipStart LLC, a semiconductor intellectual property solution company, as its US and Europe distributor for its Expresso Solution for PCI Express, Memory Interface and MIPI Solutions. ChipStart will also incorporate Northwest Logic’s memory interface products into its pre-validated memory subsystem solution called MemStart.

“I am pleased to have ChipStart be a distributor of Northwest Logic’s IP Cores in the US and Europe market. Their system-level expertise, services and proven track record are a great fit for Northwest Logic.” said Brian Daellenbach, president, Northwest Logic.

Northwest Logic provides high-performance, easy-to-use, hardware-proven IP cores including its Memory Interface Solution (DDR3/DDR2/DDR/SDR, Mobile DDR/SDR SDRAM and RLDRAM II Controller Cores), Expresso 2.0/1.1 solution for PCI Express® (x1, x4, x8 lane) and MIPI Solution (CSI, DSI).

For a complete system design, customers can use Northwest Logic’s high-performance Memory Interface Solution, including its latest DDR3/2 SDRAM controller core. The Memory Interface Solution supports a wide variety of interfaces including PLB, AHB, AXI and Multi-Port Front-End Cores, and is available for ASIC and FPGAdesigns.

About Northwest Logic

Northwest Logic, founded in 1995 and located in Beaverton, Oregon, provides highperformance, easy-to-use IP cores for ASICs and FPGAs. These IP cores include memory controller, PCI Express, PCI-X, PCI and MIPI cores. For additional information, visit www.nwlogic.com

About ChipStart

ChipStart is a semiconductor intellectual property solution company based in Palo Alto, California. ChipStart provides sales, marketing, and support engagement solutions for companies that commerce third party semiconductor intellectual property, and high quality pre-verified subsystem solutions and supporting design services for ASIC and fables semiconductor companies. ChipStart solutions are used as critical components of communications, consumer and computer products including switches, routers, modems, cellular phones, set-top boxes, HDTVs, DVD players and PCs.re information, see www.chip-start.com

# # #

Media Contacts:
Howard Pakosh howard@chip-start.com
ChipStart LLC (650) 461-9195

Brian Daellenbach Northwest Logic Inc. (503) 533-5800

Phil Casini pcasini@advancetechmarketing.com
Advanced Technical Marketing (408)375-1981

Northwest Logic and Tokyo Electron Device Enter Into A Distribution Partnership

Northwest Logic signs Distribution Agreement with Tokyo Electron Devices for its Expresso Solution for PCI Express ®, Memory Interface and MIPI Solutions

Beaverton, Oregon and Yokohama, Japan, March 18, 2009 – Northwest Logic, a leading IP Core provider and Tokyo Electron Device (TED), the leading distributor of Xilinx FPGAs have entered into distribution partnership to market and sell Northwest Logic’s IP Core Products. TED also provides a complete line of inrevium* PCI Express Boards.

Northwest Logic provides high-performance, easy-to-use, hardware-proven IP Cores including Memory Interface Solution (DDR3/DDR2/DDR/SDR, Mobile DDR/SDR SDRAM and RLDRAM II Controller Cores), Expresso 2.0/1.1 Solution for PCI Express® (x1, x4, x8 lane) and MIPI Solution (CSI, DSI).

Northwest Logic’s Expresso 2.0/1.1 Solution supports all of Xilinx’s devices including the latest Virtex®-5 FXT/LXT/SXT FPGA. Preliminary support for the Virtex-6 is also available. This solution combines Northwest Logic’s full-featured Expresso 2.0/ 1.1 Cores and software to provide a complete, pre-packaged PCI Express 2.0/1.1 solution. The latest solution enables high-performance x8 PCI Express 2.0 designs to be quickly developed for Xilinx FPGAs.

For a complete system design, customers can optionally use Northwest Logic’s high-performance Memory Interface Solution including its latest DDR3/2 SDRAM Controller Core. The Memory Interface Solution supports a wide variety of interfaces including PLB, AHB, AXI and Multi-Port Front-End Cores. This solution is available for Xilinx and ASIC designs. For more information, contact Northwest Logic at www.nwlogic.com.

“TED is very excited to be both as a solution partner and also as a distributor of Northwest Logic’s IP Cores. Northwest Logic offers high-performance products that meet the specific needs of the Japanese market. Their services and expertise will be welcome addition to our offerings.” said Yasuo Hatsumi, Director and Xilinx Product Manager, PLD Solution Division of Tokyo Electron Device.

Northwest Logic’s x8 Expresso 2.0 Solution is hardware-validated, PCI-SIG certified and available immediately for the inrevium Virtex-5 FXT PCI Express evaluation platform, TB-5V-FX70T-PCIEXP. This board and associated support package is available for immediate purchase at: http://www.inrevium.jp/eng/x-fpga-board/hibiki.html

“Northwest Logic is pleased to have Tokyo Electron Devices be a distributor of Northwest Logic’s IP Cores in the Japanese market. Their system-level expertise, services and proven track record in the Japanese market are a great fit with Northwest Logic.” said Brian Daellenbach, President of Northwest Logic.

About Northwest Logic

Northwest Logic, founded in 1995 and located in Beaverton, Oregon, provides high-performance, easy-to-use IP cores for ASICs and FPGAs. These IP cores include memory controller, PCI Express, PCI-X, PCI and MIPI cores.

Key benefits of Northwest Logic’s IP cores include:

  • High performance – support high clock rate and high throughput
  • Easy to use – simple user interface, easy to configure, etc.
  • Fully silicon validated
  • Provided with a functional verification suite
  • Support for all Xilinx FPGAs and in ASICs
  • Top quality technical support
  • Customization and integration services

For additional information, visit www.nwlogic.com

About Tokyo Electron Device

Tokyo Electron Device (TED) is a technical trading firm with a “trading business” function that provides semiconductor products and business solutions as well as a “development business” function that performs commissioned designing and the development of own-brand products.
URL: http://www.teldevice.co.jp/eng/index.htm

*About inrevium

Leveraging on rich design and development experiences accumulated at its design development center that was established in 1985, Tokyo Electron Device is focusing on development businesses through its “inrevium” brand to provide design services (commissioned designing services) based on customer requirements as well as self-developed products that anticipate future market needs. Currently, TED provides over 60 types of products and will continue to engage in the high value-added development businesses.

inrevium special site URL: http://www.inrevium.com

S2C Offers Northwest Logic IP in China

S2C Offers Northwest Logic’s High-Performance Memory Interface IP in China

Shanghai, China – March 04, 2009 – S2C Inc., a leading total solution provider in facilitating systems to chip innovations, today announced the representation of Northwest Logic Inc., a leading provider of high-performance digital Intellectual Property (IP) Cores, in China. Northwest Logic’s provides IP Cores interfacing to DDR3/2 SDRAM, RLDRAM II, PCI Express, PCI-X, PCI and MIPI. S2C will provide value-added support and services for Northwest IP core users throughout different design phases. Northwest IP cores are complementary to S2C’s existing product lines including other Silicon IP cores, rapid SoC prototyping on FPGA and eASIC devices.

Northwest Logic provides a broad range of high-performance, easy-to-use silicon IP cores optimized for use in both Application Specific Integrated Circuits (ASIC) and Field Programmable Gate Arrays (FPGA). Northwest Logic’s IP solutions include a complete Memory Interface Solution that covers all different types of DRAM support including DDR3/DDR2/DDR/SDR SDRAM, Mobile DDR/SDR SDRAM and RLDRAM II. These memory interface cores can be packaged with optional bus interface modules that interface to standards such as AXI, AHB, and PLB. The solution support many advanced features including full arbitrated multi-port support, efficiency-driven request reordering, bank management, look-ahead processing, and ECC support. All together, these features enable a multi-port memory design with different types of bus interfaces to be quickly and easily created.

“High-performance and reliable memory interfaces are critical for today’s SoC designs. We are proud to offer Northwest Logic’s memory interface IP cores which are fully silicon-proven and have been licensed by over 230 companies world-wide”, said Mon-Ren Chene, Chairman & CTO of S2C. “S2C with our expertise in rapid SoC prototyping on FPGA and eASIC solution offers two key value-added services to Northwest IP users in China. First, most designs today go through a FPGA prototyping stage. S2C provides out-of-box support for FPGA prototyping with its Xilinx Virtex-5 based TAI Logic Module and Northwest Logic IP cores. Second, for designs that need an accelerated production schedule or multiple rapid derivatives, S2C offers eASIC’s customizable, no-mask fee, no minimum order quantity ASIC devices as an early SoC production alternative. Northwest Logic also provides comprehensive eASIC devices support including an eASIC-specific DDR PHY. This DDR PHY leverages the built-in DDR I/Os and DLLs of eASIC’s Nextreme devices.”

“Despite the current economic climate, we believe China’s semiconductor industry will continue to grow at rapid pace. We are excited to partner with S2C to increase our promotion and support for our IP solutions to the Chinese designers”, said Brian Daellenbach, President of Northwest Logics. “With S2C’s strong local engineering team and spectrum of products targeting to solve SoC design challenges, we will provide our Chinese customers a one-stop user experience from design evaluation, integration, FPGA prototyping to final tape-out using Northwest IP cores.”

All Northwest cores are available today in China through S2C. For more information, please contact sales@s2cinc.com.

About Northwest Logic

Northwest Logic, founded in 1995 and located in Beaverton, Oregon, provides high-performance, easy-to-use IP cores for ASICs and FPGAs. These IP cores include memory controller, PCI Express, PCI-X, PCI and MIPI cores.

About S2C

Founded and headquartered in San Jose, California, S2C is the leading total solution provider in facilitating systems to chip innovations. S2C has four major solutions for system-on-chip (SoC) development:

  • Rapid SoC prototyping on Field Programmable Gate Array (FPGA)
  • Third-party silicon intellectual properties (IP)
  • SoC design, prototype and production services
  • Customizable, zero mask-charge, no minimum order eASIC semiconductor devices

S2C’s value proposition is our highly qualified engineering team and customer-focused sales force that understands our customers’ commercial needs in SoC development. S2C’s unique FPGA-based electronic system level (ESL) solution, using our patented TAI IP technology, enable designers easily and securely employ silicon IP to quickly assemble SoC prototypes on FPGA and immediately start software development. Combining rapid prototyping methodologies with a comprehensive portfolio of silicon IP and advanced design solutions, S2C can reduce the SoC design cycle by up to nine months.

S2C currently has 3 direct offices located in Shanghai, Beijing and Shenzhen to meet the demand for accelerated SoC design activities in China. S2C is also the organizer of the annual SoCIP seminar and exhibition in China, which brings SoC designers/professionals from the Asia-Pacific region together with international silicon IP and SoC solution vendors.

###

For more information, please contact:
Lawrence Liang, Sales Director of China Region, S2C Inc. +86 21 6887 9287, lawrencel@s2cinc.com
Lam Cheng En, Marketing Consultant, S2C Inc., +86 21 6887 9287, lamce@s2cinc.com

 


This article was originally published here:  http://www.s2cinc.com/news/news_090304.htm

Mixel and Northwest Logic Partner to Deliver a Complete MIPI IP Solution

MIPI Camera Serial Interface from Northwest Logic and D-PHY Physical Layer from Mixel now Shipping

San Jose, CA and Beaverton, OR — January 21, 2009 — Mixel Inc., the leader in mobile Mixed-Signal IPs, and Northwest Logic Inc., a leading provider of high-performance digital IP Cores, today announced the availability of a complete solution for the Mobile Industry Processor Interface (MIPI) Camera Serial Interface-2 (CSI-2). This solution consists of the Mixel MIPI D-PHY (Physical Layer) and the Northwest Logic MIPI CSI-2 Controller Core delivered as silicon Intellectual Property (IP). The companies, working together, provide customers with a complete, low-risk, low-power, low gate-count, full-featured, differentiated MIPI solution.

The Mixel D-PHY is a complete D-PHY IP, optimized for low-power operation and small foot print, and is fully compliant with the MIPI D-PHY specifications. The Mixel MIPI D-PHY is modular, and available in various configurations, up to the recommended four data lanes, each operating at 1 Gbps. The Mixel D-PHY transceiver is fully characterized, available on multiple foundry process nodes, and is in the process of being transferred to production in Mixel customer’s products. Mixel also provides its customers with the Clock Management Unit IP, incorporating a high performance, low jitter PLL and timing circuitry. The Mixel D-PHY and Clock Management Unit ship as GDSII and RTL, with LVS netlist, LEF file, Verilog and timing models, and comprehensive documentation.

“Our partnership with Northwest Logic demonstrates our commitment to providing customers with a best-in-class, total MIPI solution, and furthering our D-PHY leadership position,” said Ashraf Takla, President and CEO of Mixel, Inc. “This solution provides our customers with the best of both worlds. They not only get a proven and co-validated total solution that incorporates both the mixed-signal and digital cores, but they also get best-in-class cores that only expert IP providers like Mixel and Northwest Logic can offer” he added.

The Northwest Logic MIPI CSI-2 Controller Core implements all three CSI-2 MIPI layers including Pixel to Byte Packing Formats, Low Level Protocol and Lane Management Layer, and is fully compliant with the current version of the MIPI CSI-2 specification. The core supports transmitter or receiver operation, 1-4 data lanes, virtual channels, and all data formats. The core is specifically designed for ease-of-use, including a flexible pixel-based user interface, optional AXI and AHB interfaces, error collection support, and full configurability. The core leverages the full range of Mixel D-PHY features to ensure robust, low power operation. The core is delivered fully integrated with a Mixel D-PHY model along with a comprehensive MIPI verification environment.

“Northwest Logic is excited to partner with Mixel to offer a complete, market-leading MIPI Controller + PHY MIPI Solution. The Northwest Logic Controller Core and Mixel D-PHY have been fully integrated and validated together, to ensure robust MIPI operation. This integration, along with the comprehensive support provided by Northwest Logic and Mixel, ensure that customers can quickly develop, validate, and bring their MIPI products to market”, said Brian Daellenbach, President of Northwest Logic.

The full solution is available for customers to start chip designs today.

About Mixel

Mixel is the leader in mixed-signal mobile IPs and offers wide portfolio of high performance mixed-signal connectivity IP solutions. Mixel’s mixed-signal portfolio includes PHYs and SerDes (suitable for PCI Express, SATA, EPON, XAUI, Fiber Channel, DDR, and LVDS), Mobile PHYs (MIPI D-PHY, M-PHY, and MDDI), general purpose Transceivers, and high performance PLL, DLL IP cores. For more information contact Mixel at info@mixel.com or visit www.mixel.com.

About Northwest Logic

Northwest Logic, founded in 1995 and located in Beaverton, Oregon, provides high-performance, silicon-proven, easy-to-use IP cores including high-performance Memory Interface Solution (DDR3, DDR2, DDR, Mobile DDR SDRAM; RLDRAM II) and Express Solution (PCI Express 2.0 and 1.1 cores and drivers). These solutions support a full range of platforms including ASICs, Structured ASICs and FPGAs. For additional information, visit www.nwlogic.com.

For more information contact:

Mixel Northwest Logic
Wafa Hannaoui Brian Daellenbach
(408) 942-9300 X115 (503) 533-5800 X309
marketing@mixel.com  

Xilinx Offers First 5Gbps FPGA-Based Solution Compliant With PCI Express Version 2.0

Virtex-5 FXT FPGAs Added to PCI-SIG’s Integrator’s List as Part of Broad Solution from Xilinx Including IP, Reference Designs, Development Platforms and Characterization Reports

SAN JOSE, Calif., Nov. 20 – Xilinx, Inc. (Nasdaq: XLNX) today announced its Virtex(R)-5 FXT FPGA platform is fully compliant with version 2.0 of the PCI Express(R) standard, making it the first FPGA offering available to support the 5Gbps version of the widely-adopted serial interconnect standard. Having passed the last round of specification testing at the PCI-SIG’s Compliance Workshop #62, the Virtex-5 FXT FPGA platform has been added to the PCI-SIG(R) Integrator’s List as the centerpiece of a broad range of design resources from Xilinx and its alliance members that support PCIe(R) 2.0 applications.

With built-in 6.5Gbps Rocket IO(TM) GTX transceiver technology, Virtex-5 FXT FPGAs are ideally suited to support the PCIe 2.0 specification, which doubles the interconnect bit rate over the previous version from 2.5Gbps to 5Gbps to support leading-edge high-bandwidth applications. The recently announced Virtex-5 TXT FPGA platform, which has up to 48 RocketIO GTX transceivers, also supports the PCIe 2.0 standard. Drawing less than 150mW typical, per transceiver at 5Gbps, the RocketIO GTX transceivers enable designers to realize high-speed PCIe 2.0 performance on an FPGA with minimal power consumption.

To see a Tech-on-Line webcast on how to implement PCI Express version 2.0 compliant designs with Virtex-5 FPGAs, please visit: http://www.techonline.com/learning/webinar/211800334.

Xilinx teamed up with key alliance members to provide a comprehensive suite of design resources, including IP cores, for PCIe 2.0 multilane (x1, x2, x4, x8) support, hardware development platforms, and reference designs. These complementary offerings provide a complete, scalable and flexible solution to quickly develop systems with higher performing interconnect at lower cost to deliver first-time design success.

“The PCIe 2.0 standard offers the highest bandwidth and most power optimized version of the standard to date and is critical for high-end applications in the telecommunications and server markets where our Virtex-5 devices are widely used,” said Mustafa Veziroglu, vice president of Product Solutions Management at Xilinx. “Our long track record of supporting PCIe, and our own product strategy that includes mapping to the standard’s capabilities, enables us to offer designers a proven pathway to implement each new version of PCIe standard.”

Broad Range of Support

Xilinx Alliance Program members GDA, Northwest Logic and PLDA provide IP cores to enable PCI Express solutions on Xilinx Virtex-5 FXT FPGA devices. The Xilinx Virtex-5 FXT is the first FPGA platform to provide PCIe 2.0 x8 support, and the IP core from Northwest Logic Inc. passed the PCI Express version 2.0 compliance testing. In addition, Northwest Logic provides DMA back-end core, combining with their x8 PCIe 2.0 core to support high-performance, on-demand, multi-DMA engine operation with 3,000 Mbytes/s Card-to-System and 2,600 Mbytes/s System-to-Card throughput on Intel DX58SO platform. The Virtex-5 FXT and the newly introduced TXT silicon platforms contain the same high-performance GTX transceivers; additionally all IP and reference designs for PCIe 2.0 available for the Virtex-5 FXT platform can be easily ported to the Virtex-5 TXT platform.

The GTX serial transceivers available on both the Virtex-5 FXT and TXT FPGA platforms have been fully characterized across process, voltage and temperature (PVT), and the complete report is available for download at www.xilinx.com/support/documentation/virtex-characterization_reports.htm.

For more information on the Xilinx PCI Express solutions, go to: https://www.xilinx.com/products/technology/pci-express.html

About the Virtex-5 FXT and TXT Platforms

The Virtex-5 FXT FPGA platform is optimized for high-performance embedded processing, digital signal processing (DSP) and high-speed serial connectivity to offer the ultimate in system integration. The Virtex-5 FXT platform includes the first FPGAs to feature industry-standard PowerPC(R) 440 processor blocks. It also includes up to 24 high performance GTX transceivers capable of 6.5Gbps performance and DSP48E slices that deliver more than 190 GMAC’s of performance. The Virtex-5 TXT FPGA platform is the fifth addition Virtex-5 FPGA family and delivers twice as many 6.5Gbps GTX transceivers as the Virtex-5 FXT FPGA platform to enable 40G and 100G system in networking, telecom, audio/video broadcast and medical imaging by providing a single-chip solution for applications such as 100GbE MAC-to-Interlaken bridging.

About Xilinx

Xilinx, Inc. (Nasdaq: XLNX) is the worldwide leader of programmable logic solutions. Additional information about Xilinx is available at http://www.xilinx.com.

XILINX, the Xilinx Logo, Virtex, and other designated brands included herein are trademarks of Xilinx in the United States and other countries. PCI Express, PCIe, and PCI-SIG are trademarks of PCI-SIG and used with permission. All other trademarks are the property of their respective owners.

Editorial Contacts:
Bruce Feinberg
Xilinx WW Public Relations
(408) 879-4631
bruce.feinberg@xilinx.com

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SOURCE Xilinx, Inc.


This article originally appeared here:
http://press.xilinx.com/phoenix.zhtml?c=212763&p=irol-newsArticle&ID=1228865&highlight

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