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Building a seismic supercomputer in the shadow of Dennard Scaling

Bert Beals of Cray Inc. recently told the Digital Energy Journal that the industry can no longer simply build an efficient supercomputer for seismic processing by simply adding more processors.

Indeed, because Dennard Scaling no longer applies, advanced microprocessors now require more power and additional cooling for heat dissipation. Moreover, even though engineers might fit more transistors on a microchip, clock rates are not expected to increase significantly and transistors may have to remain dark in order to deal with thermal limitations.

Safecracking goes high-tech with side-channel attacks

During the early days of safecracking, rudimentary rotary locks were compromised by feel or sound to determine the correct combination. Following in this tradition, a security researcher known as Plore recently demonstrated how side-channel attacks can be exploited to unlock “high security” electronic safes without leaving any evidence of unauthorized access.

Smart Data Acceleration with FPGAs and DRAM

The proliferation of connected devices has significantly increased the amount of data being captured, moved and analyzed. This trend is expected to continue well into the foreseeable future as the rapidly burgeoning Internet of Things (IoT) ramps up. Perhaps not surprisingly, the exponential increase in data has created a number of new bottlenecks in data centers, prompting the industry to examine fresh approaches to system architecture.

Protecting avionic systems from side-channel attack

Asaf Ashkenazi, a senior director of product marketing at Rambus’ security division, recently sat down with Neil Tyler of NewElectronicsto discuss the potential threat side-channel attacks pose to avionic systems.

As Tyler points out, encryption is typically used to protect aerospace platforms. Although it is difficult to break the cryptographic algorithm itself, devices can readily reveal information during routine operations from such factors as power consumption, heat dissipation, time of computation and electromagnetic leaks.

ChipEstimate and Rambus look beyond DDR4

Frank Ferro, a senior director of product management at Rambus, has penned an article for ChipEstimate about the future of DRAM in the age of the IoT. According to Ferro, the semiconductor industry has traditionally relied on Dennard Scaling and Moore’s Law to ensure the creation of ever more advanced process nodes at a steady cadence.

“However, development costs at each advanced node continue to multiply as Moore’s Law begins to slow and Dennard Scaling fades into the distant past,” he explained.

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