In 1974, Robert H. Dennard co-authored a now-famous paper for the IEEE Journal of Solid State Circuits. Essentially, Dennard and his engineering colleagues observed that as transistors are reduced in size, their power density stays constant. Meaning, power use stays in proportion with area, as both voltage and current scale (downward) with length.
According to Prof. Dr.-Ing. Christian Märtin Hochschule of the Faculty of Computer Science at Augsburg University of Applied Sciences, power in CMOS chips can be modeled as dscaling. Q is the number of transistors, f the operating frequency of the chip, C the capacitance, V the operating voltage and I, the leakage current.
