Providing Layer 2 security, MACsec is becoming the predominant solution for safeguarding network traffic. While network security is increasingly a de facto requirement, there is a growing trend of protecting the SoC interfaces as well, including short distance ones such as PCI Express (PCIe) and those to off-chip memory. In this webinar, Rambus security expert, Gijs Willemse, will discuss the design and implementation of hardware-based MACsec security and trends for high-performance inline encryption.
Securing Data Center AI/ML Workloads
With the rising value of AI/ML spanning training and inference models and data, as well as the AI hardware itself, the threats from adversaries are greater than ever. As such, a security strategy for AI/ML workloads and hardware needs to offer far more than secure boot and authentication. Rambus security expert, Bart Stevens will discuss how a hardware root of trust can be the foundation for AI/ML security through defense in depth, partitioning of secure operations, and state-of-the-art protections from side channel attacks.
Selection and Implementation of a PCIe 5.0 Subsystem
The latest generation of the PCI Express, PCIe 5.0, advances performance to 32 GT/s in support of advanced applications including 400G Ethernet. In this webinar, Rambus technology experts Malini Narayanamoorthi and Vinitha Seevaratnam discuss the selection and implementation considerations for PCI Express solutions. A demonstration of the silicon-proven Rambus PCIe 5.0 interface solution consisting of integrated PHY and memory controller will be shown.
Selecting the Right High Bandwidth Memory Solution
An exponentially rising tide of data has led to the development of application-specific silicon to tackle the requirements of demanding workloads such as AI/ML training, Advanced Driver Assistance Systems (ADAS) for automotive, network graphics and HPC. To keep these processors and accelerators fed requires state-of-the-art memory solutions that deliver extremely high bandwidth. Frank Ferro will discuss design and implementation considerations of HBM2E and GDDR6 memory subsystems to address the bandwidth needs of next-generation computing applications.
Next-Generation Displays: An Integrated IP Solution from Mixel, Rambus & Hardent
Displays for next-generation smartphones, AR/VR devices, and automotive systems all require more bandwidth than ever before. Using a combination of VESA Display Stream Compression (DSC) with the MIPI Display Serial Interface (DSI-2) technology, designers can achieve display resolutions up to 8K without compromise to video quality, battery life or cost. This presentation will showcase a fully integrated off-the-shelf display IP solution consisting of Mixel (C-PHY/D-PHY Combo), Rambus (DSI-2 Controller), and Hardent (VESA DSC) IP that delivers state-of-the-art performance. Display use cases addressed by the integrated solution will be discussed. Audience Q&A follows the presentation.
CXL Memory Interconnect Initiative: Enabling a New Era of Data Center Architecture
In response to an exponential growth in data, the industry is on the threshold of a groundbreaking architectural shift that will fundamentally change the performance, efficiency and cost of data centers around the globe. Server architecture, which has remained largely unchanged for decades, is taking a revolutionary step forward to address the growing demand for data and the voracious performance requirements of advanced workloads.
