Written by Wai-Yeung Yip
Since the first iPhone was released in 2007, the world has seen and come to expect dramatic and rapid improvement in functionality and user experience from their smartphones. To make this a reality, we in the semiconductor and electronics industry are driving innovations and tremendous progress in hardware performance as exemplified by constant upgrades in performance specifications of leading application processors. To deliver memory systems that keep pace with such performance advances, we have to overcome increasing challenges in preserving both signal and power integrity of the systems while keeping power consumption in check.
When we designed the XDR memory interface, which was the memory architecture in the PS3, we designed for wide PCB manufacturing variations. The volume and cost constraints of the PS3 meant that the PCB would be manufactured by multiple vendors and that manufacturing tolerances would be large to keep the yield high. At its peak, about 15 million PS3s were shipped a year, which is a sizeable volume for any single design. Nevertheless, this volume pales in comparison with the popular smartphones of today. For example, it only took about six months for 40 million Galaxy 4S smartphones to be shipped. Imagine the kind of manufacturing variations – variations in PCB line width, layer thickness, dielectric constant, etc. – that developers have to design for to ensure a robust system in these volumes. How do we even validate the design when at most we can only test hundreds of systems?
In the report “SoC Silicon and Software Design Cost Analysis” from May 2013, Semico Research identifies a few trends in the development of SoCs using complex IP blocks. These trends include the rapid increase in the costs of integrating silicon IP in an SoC, the growing gap between SoC development cycle and what the market demands, as well as the increasing difficulty in creating first-time-right designs. Designing and validating for wide manufacturing variations is only one of many challenges driving these trends in the development of mobile memory systems with data rates approaching 2Gbps. The commoditization of smartphones is further exacerbating the problem with increasing cost pressure – for example, IDC recently reported that in 2013 the sub-$200 mobile device market grew to 42.6% of global volume, or 430 million units.
To address these challenges, Rambus has developed and is offering complex IP blocks that are robust and flexible to ease SoC and system integration efforts. These IP blocks stem from our years of mixed-signal design expertise and address the latest SI/PI challenges that arise from high-volume manufacturing of low-power, high-performance systems. Furthermore, we have developed tools to improve IP quality and accelerate time-to-market. These tools are based on advanced SI/PI methodologies which have been proven in the development of robust high-volume products.
To provide a more in-depth look at the latest trends in mobile memory, check out our white paper that discusses the challenges and solutions in both the design and validation next-generation low-power, high-performance memory systems. Join us at the Design Automation Conference (DAC) in the ARM Connected Community Pavilion located in booth #2001. At the show, you can also learn more about how we are helping our customers get to market faster with higher-quality and higher-performance products using our latest interface IPs and advanced tools. We look forward to seeing you there!