The Rambus VESA VDC-M 1.2 Encoder IP Core for AMD Xilinx FPGAs implements a fully compliant VESA Display Compression-M (VDC-M) 1.2 decoder to deliver visually lossless video compression. The decoder supports various usage models, including typical MIPI Display Serial Interface 2 (MIPI DSI-2) usage models.
Briefs
HDMI 2.1 FEC Transmitter Product Brief
The HDMI Forward Error Correction (FEC) Transmitter IP Core implements Reed-Solomon FEC and symbol mapping/interleaving as specified by the HDMI 2.1 specification.
VDC-M 1.2 Encoder for Intel FPGAs Product Brief
The Rambus VESA VDC-M 1.2 Encoder IP Core for Intel FPGAs implements a fully compliant VESA Display Compression-M (VDC-M) 1.2 decoder to deliver visually lossless video compression. The decoder supports various usage models, including typical MIPI Display Serial Interface 2 (MIPI DSI-2) usage models.
DisplayPort 1.4 FEC Receiver Product Brief
The DisplayPortTM Forward Error Correction (FEC) Receiver IP Core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA DisplayPort 1.4 specification. Forward Error Correction is required to ensure glitch-free Display Stream Compression (DSC) bitstream transport.
DisplayPort 1.4 FEC Transmitter for Automotive Displays Product Brief
The DisplayPortTM Forward Error Correction (FEC) Transmitter IP Core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA DisplayPort 1.4 specification. It contains additional safety features to detect and report transient or permanent faults in order to meet the high level of safety required by automotive applications. The IP core is ASIL-B ready, as per the ISO 26262 standard.
DisplayPort 1.4 FEC Transmitter Product Brief
The DisplayPortTM Forward Error Correction (FEC) Transmitter IP Core implements Reed-Solomon FEC and symbol interleaving as specified by the VESA DisplayPort 1.4 specification. Forward Error Correction is required to ensure glitch-free Display Stream Compression (DSC) bitstream transport.
