Download the product brief to learn how the Root of Trust CSDK enables the rapid development of secure applications for the Root of Trust RT-600 series products.
Briefs
In-Line ECC Product Brief
Part of a full suite of memory controller add-on cores, the In-Line Error Correction Coding (In-Line ECC) core works with the Northwest Logic GDDR6 and LPDDR4 Controller cores. The In-Line ECC implements the standard Hamming Code-based DRAM Single Error Correction (SEC) and Double Error Detection (DED) algorithm.
HBM2E Controller Product Brief
HBM is a high-performance memory that features reduced power consumption and a small form factor. It combines 2.5D packaging with a wider interface at a lower clock speed (as compared to DDR4) to deliver higher overall throughput at a higher bandwidth-per-watt efficiency for high-performance computing applications.
The Northwest Logic HBM2 Controller supports both HBM2 and HBM2E devices with data rates of up to 3.2 Gbps per data pin. With the Rambus HBM2 PHY it comprises a complete HBM2 memory interface subsystem.
GDDR6 Controller Product Brief
Originally designed for graphics applications, GDDR6 is a high-performance memory solution that can be used in a variety of compute-intensive applications including artificial intelligence (AI), data center and advanced driver assistance systems (ADAS).
The Northwest Logic GDDR6 Controller supports data rates of up to 20 Gbps per data pin. With the Rambus GDDR6 PHY, it comprises a complete GDDR6 memory interface subsystem.
DDR4 Controller Product Brief
The Northwest Logic DDR4 controller core is designed for high memory throughput, high clock rates, and full programmability in computing and networking applications. With the Rambus DDR4 PHY it comprises a complete DDR4 memory interface subsystem.
DDR3 Controller Product Brief
The Northwest Logic DDR3 controller core is designed for high memory throughput, high clock rates, and full programmability in computing and networking applications. With the Rambus DDR3 PHY it comprises a complete DDR3 memory interface subsystem.