The Rambus VESA® Display Stream Compression (DSC) decoder IP core deliver visually lossless video compression performance, enabling designers to handle the growing bandwidth requirements of cutting-edge displays with higher resolutions, faster refresh rates, and greater pixel depths.
Briefs
VESA DSC 1.2b Encoder for Intel FPGAs Product Brief
The Rambus VESA® Display Stream Compression (DSC) encoder IP core for Intel FPGAs deliver visually lossless video compression performance, enabling designers to handle the growing bandwidth requirements of cutting-edge displays with higher resolutions, faster refresh rates, and greater pixel depths.
VESA DSC 1.2b Encoder for AMD Xilinx FPGAs Product Brief
The Rambus VESA® Display Stream Compression (DSC) encoder IP core for AMD Xilinx FPGAs deliver visually lossless video compression performance, enabling designers to handle the growing bandwidth requirements of cutting-edge displays with higher resolutions, faster refresh rates, and greater pixel depths.
ICE-IP-339 Inline Cipher Engine with AXI Product Brief
The Rambus IME-IP-339 IME Engine can be seamlessly integrated into a customer’s system-on-chip (SOC) to address security and privacy concerns of data-in-use in DDR memory. The IME-339 provides an AXI-4 compliant wrapper around the industry-proven Rambus ICE-IP-338 (inline cipher engine). This allows the IME-339 to act as a transparent data processing pipeline on the read and write AXI data channels.
