The Rambus Temperature Sensor (TS) TS5110-G1B enables DDR5 Registered DIMMs (RDIMMs), Load Reduced DIMMs (LRDIMMs) and Non-Volatile memory DIMMs (NVDIMMs). Two TS are used per DIMM which along with the SPD Hub’s internal TS provide three points of thermal telemetry.
Briefs
MACsec-IP-361 Product Brief
The MACsec-IP-361 is a plug-and-play solution for adding MACsec on the xMII side of an Ethernet subsystem. It is ideally positioned for designs where the MAC function is tightly integrated with the system-side, for example DMA-MAC Ethernet controllers or switch core IP with integrated MAC modules.
PCIe 6.0 Retimer Controller Product Brief
The Rambus PCIe 6.0 Retimer Controller provides a highly optimized low-latency data path for signal regeneration. It supports retimer chip PHYs via PIPE 5.2/6.1 interfaces. The control plane interface is provided via CSR (AHB-lite). The PCIe 6.0 Retimer Controller is CXL protocol aware and supports links using 64 GT/s and lower data rates of PCIe.
VESA DSC 1.2b Decoder for AMD Xilinx FPGAs Product Brief
The Rambus VESA® Display Stream Compression (DSC) decoder IP core for AMD Xilinx FPGAs deliver visually lossless video compression performance, enabling designers to handle the growing bandwidth requirements of cutting-edge displays with higher resolutions, faster refresh rates, and greater pixel depths.
VESA DSC 1.2b Decoder for Intel FPGAs Product Brief
The Rambus VESA® Display Stream Compression (DSC) decoder IP core for Intel FPGAs deliver visually lossless video compression performance, enabling designers to handle the growing bandwidth requirements of cutting-edge displays with higher resolutions, faster refresh rates, and greater pixel depths.
HDMI 2.1 FEC Receiver Product Brief
The HDMI Forward Error Correction (FEC) Receiver IP Core implements Reed-Solomon FEC and symbol de-interleaving/ de-mapping as specified by the HDMI 2.1 specification.
