Bank Refresh

What is Bank Refresh?

Bank refresh refers to the periodic operation performed on individual memory banks within DRAM (Dynamic Random Access Memory) to maintain data integrity. Since DRAM stores data as electrical charges in capacitors, these charges naturally leak over time. To prevent data loss, each bank must be refreshed at regular intervals, typically every 64ms or less depending on the memory specification.

Key Features of Bank Refresh

  • Granular Control: Modern DRAM architectures allow per-bank refresh, enabling selective refreshing of memory banks rather than refreshing the entire memory array. This improves efficiency and reduces latency.
  • Concurrent Access: Per-bank refresh allows memory controllers to access non-refreshing banks while others are being refreshed, enhancing memory throughput.
  • Reduced Latency: Compared to all-bank refresh, per-bank refresh minimizes the time memory is unavailable, which is critical for real-time and high-performance applications.
 

Benefits

  • Improved System Performance: By allowing concurrent operations during refresh cycles, per-bank refresh reduces bottlenecks in memory access.
  • Lower Power Consumption: Refreshing only the necessary banks conserves energy, especially in mobile and embedded systems.
  • Enhanced Scalability: Supports advanced memory configurations in multi-core processors and AI accelerators.
 

Enabling Technologies

  • DDR4/DDR5 and LPDDR4/LPDDR5 Standards:
    These memory standards support fine-grained refresh mechanisms, including per-bank and targeted refresh modes.
    https://www.jedec.org/standards-documents/docs/jesd79-5a
  • Memory Controllers with Refresh Scheduling: Advanced memory controllers implement refresh scheduling algorithms to optimize timing and reduce interference with active memory operations.
  • Self-Refresh and Auto-Refresh Modes: DRAM devices can enter self-refresh mode during low-power states or use auto-refresh triggered by the controller.
 

Rambus Technologies in Bank Management

Rambus offers memory interface IP that supports advanced refresh management, including per-bank refresh scheduling for DDR and LPDDR memory systems. These features are critical for applications in automotive ADAS, AI inference, and high-performance computing, where memory availability and efficiency are paramount.

Rambus logo