PCI Express 4.0 Core
Northwest Logic is now offering PCI Express Gen 4 support as part of its high-performance PCI Express solution. Northwest logic’s PCI Express solution has been widely deployed in cutting edge ASIC and FPGA designs. Some of the key features of the PCI Express 4.0 Core include:
- Endpoint, Root-Port, and Switch support
- 16 Gb/s, 8.0Gb/s, 5.0 Gb/s, 2.5 Gb/s line rate support
- x16, x8, x4, x2, x1 PCI Express Lane support
- Bifurcation support
- High Reliability – AER, ECRC, ECC, and Parity support
- Multi-Function and SR-IOV support with up to 256 total Functions
- Flexible PIPE interface can support all PIPE compatible PHYs
- High-performance AXI Bridging and DMA solutions support
This solution is available for standard cell ASICs, Structured ASICs and FPGAs. Please contact email@example.com for more information
Northwest Logic’s DMA Core is Now Included in Vivado 2015.1 IP Catalog
Northwest Logic’s high-performance, scatter-gather AXI DMA Back-End Core is now included in the latest release of the Vivado IP catalog. This support enables our Xilinx customers to easily integrate the NWL DMA Core into their design as part of the IP integrator flow. The AXI DMA Back-End Core is part of a larger offering of high-performance DMA Cores from Northwest Logic. Contact firstname.lastname@example.org for more information.
Complete CSI-HDMI Demo
Northwest Logic and Mixel have created a new CSI-HDMI demo. This comprehensive demo takes 4K video output from Omnivision 13850 camera (4 MIPI lanes running at 1.2 Gbit/s). This CSI video stream is then processed by the combination of Mixel D-PHY Test Chip and Northwest Logic’s CSI Controller Core running in a Virtex-7. The video stream is then formatted and sent via HDMI to a 1080P display. Click here to see the demo on YouTube.
HBM Gen 2 Controller Coming Soon
High Bandwidth Memory (HBM) enables a system to achieve significantly higher memory throughput than a DDR4-based system. HBM is a 2.5D based solution where 8 channels of 128 bit memory are connected to an ASIC using a silicon or organic interposer. Each channel can be further subdivided into two 64-bit pseudo-channels. Northwest Logic will be releasing its HBM Gen 2 Controller including Pseudo Channel and IEEE 1500 support shortly. Contact email@example.com for more information.
Northwest Logic and S2C Deliver Hardware Validated MIPI Solution
Northwest Logic and S2C, Inc. announced that Northwest Logic’s Mobile Industry Processor Interface (MIPI) Camera Serial Interface (CSI-2) Controller and Display Serial Interface (DSI) Controller have been fully validated on S2C’s FPGA Prototyping Platforms. Click here to see press release.
RLDRAM 3 Solution Availability for Arria 10
Northwest Logic and Altera Corporation have collaborated to release a hardware-proven 2,133 Mbps Reduced Latency DRAM (RLDRAM®) 3 memory interface solution for use in the 20 nm Arria® 10 FPGAs. The RLDRAM 3 memory interface solution combines Northwest Logic’s full-featured RLDRAM 3 Controller Core and Altera’s auto-calibrated RLDRAM 3 HardPHY to significantly ease RLDRAM3 designs for high-end networking applications needing high memory throughput. Contact firstname.lastname@example.org for more information.
Visit Northwest Logic at DAC
Northwest Logic will be at DAC 2015. Visit us in the Mixel booth or TCI booth. We are also happy to setup a private meeting with you ahead of time. To set up a meeting to discuss your PCIe, memory or MIPI design needs, please send an email to email@example.com
Customer Testimonial: QuintessenceLabs
QuintessenceLabs has recently rolled out its latest Key Manager product which uses Quantum Random Number Generator (QRNG) to generate unique keys for encryption and decryption. QRNG uses vacuum fluctuation in quantum optics to produce raw entropy that is extremely fast and very stable. To transfer the large amount of random numbers, Quintessencelabs employs the Northwest Logic AXI DMA Back-End core to consolidate multiple numbers of high speed DMA sources into a single PCIe DMA channel. “This IP core is stable, and integrates seamlessly into our proprietary logic without needing support. As a result, it allowed us to speed up the prototyping cycle and reduced the product development time line significantly.” Said Dr. Raymond Chan, Principle Engineer at QuintessenceLabs