Northwest Logic’s Second Generation HBM2 Controller Core Now Available
Northwest Logic’s first generation HBM2 Controller Core (V1) is the HBM2 market leader with 19 HBM2 customer design wins, 7 test chips, and 100% first time tapeout silicon success. Northwest Logic’s second generation HBM2 Controller Core V2 heavily leverages the V1 core. The V2 core supports currently available HBM2 devices as well as future channel densities (6, 12, 16, 24 Gbits) and speeds (2.8, 3.2 Gbit/s/pin). In addition, the V2 core consumes 30% less silicon area compared to the V1 core. “We look forward to meeting the growing needs of data intensive memory applications with our second generation HBM2 Controller Core V2 solution”, said Brian Daellenbach, President of Northwest Logic. For more information about Northwest Logic’s HBM2 Controller Core V2, click here.
Northwest Logic and NetSpeed Partner to Boost Performance in Hyperscale and Automotive SoCs
Northwest Logic and NetSpeed have partnered to deliver high throughput memory subsystem solutions for customers designing SoCs for hyperscale and automotive applications. The combination of NetSpeed’s interconnect IP and Northwest Logic’s HBM2 and GDDR6 memory controllers provides a platform that enables end-to-end QoS (Quality of Service), resiliency and high performance. “NetSpeed’s market leadership in the hyperscale and automotive segments is strengthened through our partnership with Northwest Logic,” said Anush Mohandass, VP of Marketing and Business Development at NetSpeed. “Our integration with Northwest Logic provides customers end-to-end QoS and end-to-end resiliency that is needed for next-gen applications.” For more information about Northwest Logic’s memory controllers, click here. To view the full NetSpeed press release, click here.
Aldec’s HES UltraScale+ Reconfigurable Accelerator and Northwest Logic’s PCI Solution
Aldec, Inc., a pioneer in mixed-HDL language simulation and hardware-assisted verification for ASIC and FPGA designs, has used Aldec’s HES-XCVU9P-QDR UltraScale+ board with Northwest Logic’s Expresso 3.0 core for PCI Express® and AXI DMA Back-End Core to demonstrate a proven PCI Express solution which provides over 6 GB/s PCI Express throughput. “Several of our customers developing High-Performance Computing (HPC) applications such as those for High Frequency Trading (HFT) and Genome Alignment require easy to use PCIe core with a high throughput”, said Louie De Luna, Director of Marketing. “Northwest Logic’s Expresso 3.0 solution with high-performance scatter-gather DMA support is ideal for the various Endpoint, Root Port, Dual Mode and Switch use cases of our customers.” Click here for the full press release.
Northwest Logic Utilizes Avery Design’s Memory Models to Validate Its HBM2 and GDDR6 Controller Cores
Northwest Logic utilizes Avery Design’s full featured memory models to validate its memory controller cores including HBM2 and GDDR6. “Avery Design’s memory models are a key component in our overall memory controller validation strategy. Their models emulate the various memory devices available from the memory vendors. This enables the performance of various memory devices to be easily compared. In addition, Avery Design provides early releases of its models as the standards are evolving and responsive model support,” stated Brian Daellenbach, president of Northwest Logic. Please contact Northwest Logic or Avery Design for more information.
Northwest Logic Automates CDC and RDC Verification Using Questa CDC and Questa Reset Check
Northwest Logic uses Questa® CDC and Questa Reset Check during its core development and deliveries to comprehensively verify that its cores properly handle clock domain crossings (CDC) and reset domain crossings (RDC). To perform this verification efficiently and accurately, Northwest Logic has automated the process of utilizing Questa CDC and Questa Reset Check in its regression flow. This automation is accomplished using a script-based process to extract and configure the cores in Northwest Logic’s code repository and run CDC and RDC regression tests on them. “Northwest Logic’s verification environment utilizes a full suite of Questa tools to comprehensively and efficiently verify our controller cores,” said Brian Small, Infrastructure lead, Northwest Logic. To view the full CDC/RDC automation success story please follow this link.
Northwest Logic Will Be Participating in the Samsung Foundry Forum
Northwest Logic, a Samsung HBM Ecosystem Partner (see white paper), will be participating in the Samsung Foundry Forum on May 22, 2018 at the Santa Clara Marriott. Northwest Logic’s market leading HBM2 Controller Core is available for use in Samsung Foundry’s advanced process nodes. “Our collaboration with Samsung ensures that our customers achieve the highest possible system performance when using the combination of Northwest Logic’s HBM2 Controller IP and Samsung’s HBM2 devices,” said Brian Daellenbach, President at Northwest Logic. Please stop by Northwest Logic’s kiosk to learn about Northwest Logic’s HBM2 and other controller cores for your next Samsung Foundry design.
Northwest Logic Will be at Design Automation Conference (DAC) 2018
Northwest Logic will be at DAC 2018 in San Francisco, June 26th and 27th. Please contact us if you are going to be at DAC and would like to have a face-to-face meeting to discuss our latest Memory, PCIe or MIPI IP products and roadmap. We will also be periodically present in several partners’ booths including Mixel (Booth #1323) and Analog Bits (Booth #1652).
