HBM2 Update From Northwest Logic and eSilicon
eSilicon and Northwest Logic have been collaborating on 2.5D HBM designs for several years, starting with an FPGA, HBM1, organic interposer-based design more than five years ago. Since then, eSilicon has created a high-performance HBM PHY and taped out several multi-project wafer runs for silicon IP validation, improved manufacturability, test, reliability and yield enhancement. Northwest Logic has created a full featured HBM Controller Core which provides high performance across a broad range of traffic scenarios. The controller and PHY have been silicon-verified in planar and FinFET processes using large and stitched (extra large) silicon interposers integrated with the DRAM stacks in 14nm and 28nm HBM2 test chip designs. Customer ASIC’s which use this HBM2 controller and PHY combination are moving into production in 2017.
Northwest Logic Delivers Next Generation DSI-2 Controller Cores
Northwest Logic has made initial customer deliveries of its MIPI DSI-2 Controller Cores. The DSI-2 Host and Peripheral Controller Cores are available in 64 and 32 bit widths maximizing ease of use and flexibility. The cores support up to four 2.5 Gbit/s D-PHY lanes or up to four 2.5 Gsym/s C-PHY lanes (trios). The cores are delivered fully integrated with the customer’s target MIPI PHY (D-PHY, C-PHY or combo D/C-PHY). For more information on the latest DSI-2 standards see the Northwest Logic and Mixel MIPI DEVCON presentation. For more information on the DSI-2 Controller Core, click here
Analog Bits, Northwest Logic And Avery Designs Create a Complete Eco-system Solution For PCI Express® (PCIe®) 4.0
Analog Bits, Northwest Logic and Avery Designs have joined forces to create a complete eco-system solution for PCI Express 4.0 designs. To achieve this, Northwest Logic’s PCIe 4.0 Controller Core has been integrated with the Analog Bits PCIe 4.0 PHY and verified using the Avery VIP for PCIe 4.0. This PCIe 4.0 solution supports 16/8/4/2/1 lane operation with bifurcation at 16/8/5/2.5 Gbit/s line rates. This solution has been delivered for a TSMC 16nmFF process customer design. This fully integrated solution enables customers to confidently create PCIe 4.0 based designs for their SOCs now. Click here for more information.
Northwest Logic MIPI Solution Now Supports Intel Programmable Solutions Group (PSG) Arria-10 Devices
Northwest Logic has released support for Intel PSG Arria-10 devices and customer deliveries of our MIPI CSI-2 and DSI/DSI-2 controller cores. “Northwest Logic is a Platinum member of Intel Programmable Design Solutions Network. We are pleased to continue our close collaboration with Intel PSG. We look forward to supporting Arria-10 customers with our high quality and easy to use MIPI Controller Cores. These cores operating in the Arria-10 can support CSI-2 and DSI/DSI-2 designs with D-PHY lane rates up to 1,500 Mbit/s.” said Brian Daellenbach, President of Northwest Logic. For more information about our MIPI solution please visit. “We are pleased to see Northwest Logic’s continued engagements in the Intel FPGA Design Solution Network (DSN)” says Michael E. Sharpless, Intel FPGA Partner & Solutions Marketing World Wide Program Manager. For more information on Altera’s DSN, please visit.
Philips Innovation Services Success With Northwest Logic CSI-2 Rx Controller Core
Philips Innovation Services has leveraged Northwest Logic’s MIPI compliant CSI-2 Rx Controller core for a 78 GHz Automotive Radar System. “The Northwest Logic CSI-2 Rx Controller core solution was easily integrated into our system simulation environment. Deployment in our FPGA-based design environment exceeded our expectations. Northwest Logic’s professional technical support and easy to use IP were a fundamental part of our success.” said Ben Zwaans HW Architect of Philips Innovation Services. This is another example of how the MIPI Alliance standards have created an eco-system that has expanded well beyond the traditional mobile phone market. For more information see our MIPI Solutions web page.
Northwest Logic Provides DDR2 Solution For Virtex-5QV Devices
Northwest Logic provides a complete DDR2 Controller and PHY solution for Virtex-5QV devices. Northwest Logic’s DDR2 solution is a full featured, modular solution that can be configured to exact customer requirements. The rad-hard Virtex-5QV devices provide immunity for single event latches upset (SEU), total immunity to single-event latch-ups (SELs), total ionizing doses (TIDs) and datapath protection from single-event transients (SETs). “We are pleased to have Northwest Logic’s DDR2 Memory Controller as part of our Virtex5QV solution” Daniel Elftmann, Product Manager for Xilinx Rad-Hard devices. Northwest Logic’s DDR2 solution has been fully verified and hardware validated with the Virtex-5 ML510 Platform. Contact Northwest Logic for more information.
Mentor Graphics, Northwest Logic, and Krivi Semiconductor Announce Availability Of Complete DDR4 SDRAM IP Design And Verification Solution
Mentor Graphics® Corporation (NASDAQ: MENT), Northwest Logic and Krivi Semiconductor today announced the availability of a complete DDR4 SDRAM IP design and verification solution that enables ASIC and FPGA design teams to quickly design and verify DDR4 memory subsystems in the Mentor Graphics IP Partnership Program. Together, Mentor Graphics, Northwest Logic, and Krivi Semiconductor enable customers to reduce time-to-market by a factor of 2X by integrating complementary design and verification IP into a single flow. Northwest Logic provides silicon-proven, high-performance, easy-to-use memory controller design IP for use in both ASICs and FPGAs along with a comprehensive set of add-on cores, while Krivi Semiconductor offers state-of-the-art DDR PHY with DFI compatibility and minimum integration overhead. Mentor Graphics supplies a comprehensive, configurable, ready-to-go verification IP tool suite for memory controllers and interfaces. Click here for more information.
