eASIC Based DDR2 SDRAM Solution Provides 60% Higher Performance than Mainstream Low-Density FPGAs
Santa Clara, CA – June 30, 2008 – eASIC Corporation, a provider of zero-mask charge ASIC devices, and Northwest Logic, a provider of high-performance IP Cores, today announced the immediately availability of a silicon-proven 533 Mbps DDR2 SDRAM solution for eASIC’s low-cost Nextreme family of devices. The combination of eASIC’s Nextreme and Northwest Logic’s DDR2 SDRAM Memory Interface Solution provides 60% higher performance than mainstream low-density FPGAs, which are typically limited to 333 Mbps or less performance. The solution utilizes Northwest Logic’s high-performance DDR2 SDRAM Controller Core and eASIC-specific DDR PHY to provide an easy-to-use, one-stop-shop solution for eASIC’s Nextreme devices.
Northwest Logic’s DDR2 SDRAM Memory Interface Solution combines Northwest Logic’s high-performance, fully featured DDR2 SDRAM Controller with its eASIC-specific DDR PHY. This DDR PHY leverages the built-in DDR I/Os and DLLs of eASIC’s Nextreme devices. The solution includes a variety of add-on peripherals including AHB/AXI Interface, Multi-Port Front-End and ECC Cores, which make it straightforward to integrate with other sub-systems. Northwest Logic’s eASIC-based DDR2 SDRAM Interface Solution has been fully characterized to support robust 533 Mbps DDR2 SDRAM operation. Contact Northwest Logic for a detailed characterization report.
“eASIC’s Nextreme solution offered us an excellent blend of cost and performance. We could not achieve the memory bandwidth nor the cost point we needed in a FPGA,” said Sunny Ng, Vice President of Engineering at Aurora Systems. “The combination of eASIC’s Nextreme devices and Northwest Logic’s Memory Interface Solution is an excellent fit for our consumer video applications.”
“Northwest Logic has a solid track record of delivering memory interface solutions. The addition of its DDR2 SDRAM Memory Interface Solution to our eZ-IP Alliance portfolio, and its outstanding technical support will provide our customers peace-of-mind when implementing memory interfaces onto our eASIC Nextreme devices,” said Jasbinder Bhoot, Senior Director of Marketing at eASIC.
“We are very pleased to make our Memory Interface Solution available for the eASIC Nextreme devices. This combined solution enables customers to quickly implement and bring a high-performance, cost-effective SOC solution to the market,” said Brian Daellenbach, President of Northwest Logic.
About eASIC
eASIC is a fabless semiconductor company offering breakthrough zero mask-charge ASIC devices aimed at dramatically reducing the overall cost and time-to-production of customized semiconductor devices. Low-cost, high-performance and fast-turn ASIC and System-on-Chip designs are enabled through patented technology utilizing Via-layer customizable routing. This innovative fabric allows eASIC to offer ASICs with no mask-charges and no minimum order quantity.
Privately held eASIC Corporation is headquartered in Santa Clara, California. Investors include Khosla Ventures, Kleiner Perkins Caufield and Byers (KPCB), Crescendo Ventures, Advanced Equities Incorporated and Evergreen Partners. For more information, please visit www.eASIC.com.
About Northwest Logic
Northwest Logic is located in Beaverton, Oregon and provides high-performance, easy-to-use, silicon-proven IP cores for FPGAs, Structured ASICs and ASICs. These IP cores include memory controller, PCI Express and PCI cores.
Key benefits of Northwest Logic’s IP cores include:
- High performance – support high clock rate and high throughput
- Easy to use – simple user interface, easy to configure, etc.
- Fully silicon validated
- Provided with a comprehensive verification suite
- Support for eASIC’s Nextreme platform, standard cell ASICs and FPGA prototyping
- Top quality technical support
- Customization and integration services available
For more information please contact info@nwlogic.com or visit www.nwlogic.com
Contact
Spencer Horowitz for eASIC Corporation
spencerh@ieee.org
Tel: (408) 832-9616
www.eASIC.com
This article originally appeared here: